In one of the five chip-design repositories we opened today, there is a decision record in which the agents working on a voltage regulator conclude that their own measurements had not been measuring the thing they were named after. The numbers were real. What they were evidence of was a question nobody had checked.
The five blocks are gf180-ldo, gf180-pll, gf180-sar-adc, gf180-trng and gf180-temp-por: a low-dropout regulator, a phase-locked loop, a 10-bit SAR ADC, a true random number generator, and a temperature sensor paired with a power-on reset. All target gf180mcu, GlobalFoundries' open 180 nm process. All are designed by agents running an open-source flow, xschem for schematics, ngspice for simulation, klayout-tools for layout. They join the two bandgap references we opened in July.
None is finished and one, on paper, just got considerably worse. Publishing a working block is easy. Publishing an unfinished one is where the append-only records and the decision records either hold or turn out to be decoration.
The measurement that turned out not to be one
The LDO's job is to hold its output steady, and the usual way to ask whether a feedback loop will do that rather than oscillate is to measure phase margin: how much extra delay the loop could absorb before it starts fighting itself. The project's ratified spec, DR-0001, wants at least 45 degrees of it at every combination of process, voltage, temperature, load, output capacitance and series resistance in the matrix it enumerates.
Early results failed and then improved, a compensation change carrying the worst corner from roughly −13 degrees to −1.26, and a later recompensation taking the passing count to 2689 of 3240 points. That number never became the headline it was on its way to becoming, because issue #53 then found that the error amplifier inside the loop oscillates on its own. Loop gain with right-half-plane poles is the case where a phase-margin reading stops meaning what the textbook says it means, and no loop-stability record in the repository had ever tested for it. DR-0008 records the finding and applies it to the project's own prior work: 2689 of 3240 passing is, on that reading, not a stability claim at any load. It is still a proposal no operator has ratified, and the repository is acting on it anyway. Issue #51 still leads with the stale table, and the section under it is a header telling readers to read the correction before the numbers above.
The compensation was reworked, and the current verdict record reports 1332 of 4536 points passing DR-0001, on a matrix that grew when resistor corners were added. No point in the 4536 shows the frequency-domain signature that had invalidated the earlier readings. The record declines to read that as the all-clear: it calls the row necessary-but-not-sufficient and leaves sim/amp-selfosc/, which measures the oscillation directly in the time domain, as the load-bearing check. A worse headline number than the one it replaced, arrived at honestly. The superseded records are still in the repository rather than tidied out of it.
The loop that did not lock
The PLL keeps its evidence the same way, 52 simulation records across 18 verification campaigns, and its first closed-loop run is in there as a failure. Record 20260801-085349-0e5c22d fails four of seven checks: residual frequency error at 1.84e−3 against a bound of 1e−3, static phase error of 14.05 ns against a 2.22 ns allowance, and a loop that had not converged when the transient stopped at 20 µs.
The feedback divider passed, 7.99988 against a target of 8, which is what makes the record useful rather than merely discouraging. The working parts are separable from the broken one, so the open issue inheriting this record gets a design question, whether to extend the transient or retune the loop, instead of a verdict that the block does not work. The record went in while its headline verdict was still FAIL.
When the tooling was wrong
The same repository's sim/README.md names an awkward case: a nine-corner supply-sensitivity result taken with a simulator timestep looser than a bound the project adopted later. The available moves are to re-run it quietly or to void everything measured under the bad setting.
Record 20260801-114140-f87afc5 does neither. Five of the nine rows carry the artifact's signature and are qualified rather than retracted, recorded as not evidence about this design. The other four stand, on the argument that too coarse a timestep can only manufacture a failure and never conceal one. An integrator that is dropping detector pulses cannot make a loop look like it is holding the right frequency at the independently predicted control voltage. That asymmetry is what lets the record qualify five rows without discarding the grid. Adjudicating your own prior results row by row is more work than re-running them, which nobody would have noticed you skipping.
Labels that admit what they are
The TRNG's ratified spec table has rows that are not measurements. Its raw min-entropy figure, 0.5 bits per sample, is a design target, and the cell says so, next to the corner where it would have to hold and the issue that still owes the simulation. The SAR ADC's README is blunter. It says there is no ADC yet, only "the substrate you need before there honestly can be one". The temperature sensor is at a similar stage and its README says so: a DRC and LVS flow proven clean on exactly one real cell, with the sub-circuits inside the hierarchy still placeholders.
None of these blocks has been fabricated. One currently passes under a third of its own stability matrix, and got there by discovering that its previous, better-looking numbers were answering a different question. We would rather publish that than the version that reads well, and the test of whether the conventions are real is what they cost when a result goes the wrong way. So far they have cost a headline number and a day of re-measurement, which is cheap at this stage and will not stay cheap.