What happened yesterday in AI chip design, EDA, open silicon, and hardware/software codesign.
Intel licensed Atom-class x86 core RTL to a startup
Intel is reportedly sharing Atom-class core RTL with RosaicLabs, letting an outside company build its own custom x86 processor. x86 RTL has effectively never been licensable — if this holds, it is a structural shift in who can build x86 silicon, and Chips and Cheese connects it to a curious 32-tile AMX configuration that suggests a many-core inference part. Worth watching as a signal that even the most closed ISA franchises are opening under AI-era pressure. Tom's Hardware via r/hardware · Chips and Cheese analysis
ChipAgents raised $134M for agentic AI in EDA
ChipAgents' CEO discussed what a $134M round buys for their agentic-AI EDA offering. The size of the round is the story: investors are now funding agent-driven chip design tooling at a scale previously reserved for silicon itself. Adjacent signal from the same day: Wally Rhines on EDA AI trends, and r/chipdesign discussing Razavi's webinar on AI in analog design — the AI-in-EDA conversation is running across every layer of the field at once. TechTechPotato interview
An open-source RFIC design flow, shown end to end
The day's top r/chipdesign post (115 points) walks through an RF IC design flow built on open-source tools. RF has long been the "you need Cadence" holdout; a documented open flow reaching RFIC is another domain where the open toolchain is becoming practically usable, not just pedagogically interesting. r/chipdesign
Two new papers on LLMs doing RTL work
ARES (arXiv) steers the reasoning effort of LLM agents doing PPA-aware RTL optimization — treating inference cost as a first-class constraint in the edit-synthesize-analyze loop. Separately, a benchmark from NMIMS/IIT Roorkee/BITS Pilani evaluates open-source LLMs across 50 Verilog design-flow tasks. The research front is moving from "can an LLM write Verilog" to cost-aware agent loops and systematic evaluation — the same shape the software-agent world took a year earlier. ARES · Verilog benchmark via SemiEngineering
New project: copperhead — "Cursor for circuit boards"
A new repo (37 stars in its first days) pitches itself as Cursor for circuit boards. Early and unproven, but the framing alone is notable: the agent-native-EDA category is now attracting independent builders, not just research groups and incumbents. github.com/chouhanindustries/copperhead
The AI silicon crunch, in three data points
Samsung posted a >250-fold rise in Q2 chip profit and expects the shortage to run into 2028; Nvidia consumer GPU prices rose up to another 30%; and TSMC added $100B to its Arizona plans. Three separate stories, one structure: AI demand is absorbing fab capacity years forward, which shapes everything from memory pricing to who can get advanced-node access at all. Samsung via r/hardware · Nvidia pricing · TSMC Arizona
Tenstorrent shipped tt-metal v0.75.0
A stable release of Tenstorrent's open-source low-level software stack for its AI accelerators. Routine on its own, but tt-metal is one of the few places where a full accelerator software stack is developed in the open, which makes its release cadence a useful proxy for how fast the open AI-hardware ecosystem iterates. Release notes
Openchip announced BER10, a RISC-V chip for AI/HPC
Openchip introduced BER10, a RISC-V part aimed at AI, HPC, and critical infrastructure. Another entry in the growing class of serious RISC-V compute silicon — the ISA's move upmarket from microcontrollers continues. HPCwire via r/RISCV
Also noted
- CXMT's founder pledged $5.6B in worker bonuses after the China memory maker's IPO — r/hardware
- Photonics moving into the package: co-packaged optics to nanolasers (CEA-Leti, Scintil, NcodiN) — EE Times
- 2D p-type semiconductors + oxide n-channel for complementary BEOL CMOS (Stanford/Hanyang) — SemiEngineering
- r/RISCV discussing a claimed China roadmap from 3nm to 1.4nm-equivalent by 2031 — thread
- RISC-V International on extension migration across spec, hardware, and software — blog
- Pushing the limits of RISC-V emulation with a recompiler — blog via r/RISCV
- Wally Rhines on his first year as Silvaco CEO and EDA AI trends — video
- New project: rtl-nic, source-available SystemVerilog RTL for a custom FPGA Ethernet datapath — repo
- New project: NPU-E2E, an end-to-end NPU from RTL systolic array through AXI4 SoC to a TVM compiler on FPGA — repo
- Warpage management getting harder in advanced packaging — SemiEngineering
- Hybrid NAND+DRAM memory device proposed (U. of Seoul) — SemiEngineering
- r/FPGA asking whether Lattice acquired AMI — community discussion, unconfirmed — thread
90 items considered: 53 Reddit · 15 arXiv · 15 RSS · 7 GitHub · 0 HN. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.