What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Qwen shipped a model launch with an RTL-to-layout run in the release notes
Qwen3.8-Max landed on August 2, and one of the three headline case studies in its announcement is an autonomous chip design flow. Given a task description, a stub RTL workspace of empty module templates, and an evaluation script — no golden reference design, no human in the loop — the model drove a GCD/RSA cryptographic accelerator through roughly 500 turns and 71 evaluations, holding bit-exact correctness under randomized cocotb verification across 4-, 6-, 8-, and 16-bit widths while cutting the synthesized gate count from 8,298 to 678. It then ran the result through place-and-route and reports timing closure at 500 MHz with the die shrinking from 106×106 to 46×46 µm² and wirelength falling from 33,369 to 4,187 µm.
The detail worth sitting with is the toolchain: Iverilog for simulation, Yosys for synthesis, OpenROAD on Nangate45 for physical design. The open silicon stack is what a frontier lab reached for when it wanted to demonstrate hardware capability in a launch post — not a licensed commercial flow. These are vendor-reported numbers on a single small block, unreplicated, and the claim of "leading all evaluated models" comes with no comparison table. Note also that the r/FPGA thread that surfaced this describes it as a SystemVerilog highlight; the page does not use that word anywhere. Qwen3.8-Max release notes · r/FPGA
Someone finally measured how bad RTL training corpora are
RTLCurator reports that in two widely used RTL datasets, only 24.4% and 53.5% of spec/code pairs pass generated functional tests — most public RTL corpora are synthesized, and synthesis gives scale without correctness. The paper's argument is that filtering on correctness alone is the wrong fix, because it strips out exactly the long sequential designs that are hard to generate, leaving a corpus of short simple modules. Their method keeps 80% of a corpus while validating only 10% of it, and beats training on the full corpus on every reported metric. The same window saw an RTL debug benchmark, an RTL example set, and a Verilog chain-of-thought dataset all land on Hugging Face — data quality, not model size, is where this subfield is currently spending its effort. RTLCurator · rtl-debug-bench · rtl-examples · Verilog-CoT-Dataset
Granite verifies RTL processors against ISA contracts, timing included
MIT, Google, and the University of Washington published a modular methodology for proving both functional correctness and nonleakage of RTL processors against ISA contracts. The claim that matters is the timing one: they prove the cycle-by-cycle timing of a pipelined RISC processor, not just its architectural end state. Leakage contracts have mostly lived in paper models of processors; pushing them down to actual RTL, modularly, is the direction that would make them usable during design rather than after. SemiEngineering
SpiNNaker2 published, aimed between neuromorphic and deep networks
TU Dresden and the University of Manchester put out the technical paper for SpiNNaker2, a many-core platform they describe as bridging deep networks and neuromorphic computing, reporting up to 4.5 TOPS. SpiNNaker has been running as a large academic architecture program for years, so the paper is a checkpoint on real silicon rather than a proposal. Worth reading for anyone who thinks the accelerator design space collapsed to systolic arrays and HBM. SemiEngineering
China reportedly building its own immersion DUV steppers
A widely-discussed r/Semiconductors thread (36 points) reports domestic immersion DUV tool production starting this year — five units, 28nm class. Five units is a pilot line, not a supply chain, and the report is secondhand. But immersion DUV is the specific chokepoint that export controls were built around, so even a small confirmed domestic capability changes the long-run shape of who can access what process node. r/Semiconductors
Open toolchain releases: Magic 8.3.679 and Veryl v0.20.3
Magic, the layout editor at the base of the open sky130 flow, tagged 8.3.679 with extraction and extresist fixes. Veryl — the Rust-flavored HDL that compiles to SystemVerilog — shipped v0.20.3 and drew posts in both r/chipdesign and r/FPGA. Neither is a large release. Both matter as cadence signals: the open toolchain's maintenance rhythm is what determines whether it is usable for real work or only for demos. Magic 8.3.679 · Veryl via r/chipdesign · Veryl via r/FPGA
Analog compute-in-memory hits the KV cache problem
Analog CIM works well for weight-stationary linear layers, which is where most of its published wins come from. This paper takes on attention, where KV cache operations need repeated in-situ weight updates and so run straight into hardware noise. The finding is token-level: sink tokens and recent tokens are disproportionately noise-sensitive, so the authors keep those on a higher-precision digital path and let the rest go analog. That shape — profile which part of the workload actually tolerates the analog substrate, then split the datapath — is the recurring pattern in making exotic compute usable. arXiv
Also noted
- SiFive says its P870-D, a datacenter-class RISC-V CPU IP, is in real silicon with customers — via r/RISCV
- Helios reportedly took the HBM bandwidth lead from Rubin — r/hardware
- Lexar shipping DDR5-7200 built on Chinese DRAM — r/hardware
- AirLLM runs 70B inference on a single 4GB GPU via layer-wise offload — HN
- Chips and Cheese on Arm's Cortex A55, the efficiency-first 5-series core — analysis
- IREE cut 3.12 release candidates two days running — release
- New crate: guarded-continuation-checker, proof-carrying bounded verification for embedded firmware and RTL — crates.io
- New crate: kicad-auto-importer, watches a folder for part-provider downloads and imports them into a KiCad project — crates.io
- ProtoOS, a security-focused RISC-V OS, posted a three-month showcase — r/RISCV
- All 25 FPGA Horizons London talk videos released free ahead of the event — r/FPGA
- ICCAD 2026 notifications expected in about a week — iccad.com
- ASPLOS 2027 CFP deadline approaching, roughly four days out — asplos-conference.org
- Why RISC-V disassemblers refuse to decode extensions absent from ELF attributes — r/RISCV
- A PLL for n-type-only IGZO thin-film transistors, for flexible electronics where no p-type device exists — arXiv
- Automotive sensors are aging faster than the safety cases assume — SemiEngineering
97 items considered: 36 crates.io · 26 Reddit · 17 Hugging Face · 6 RSS · 5 arXiv · 4 GitHub · 2 conferences · 1 HN · 0 OpenAlex · 0 PyPI. Adapter failures: Bluesky (all 10 searches returned HTTP 403 — the public search endpoint now appears to require authentication), USPTO patents (no API key configured). Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.