What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Yosys 0.68 adds symbolic floating-point passes and drops flowmap
The release adds symfpu and symfpu_convert passes. The release notes name them without describing them; SymFPU is an established library for encoding IEEE-754 arithmetic into bit-vectors so SMT solvers can reason about floating point, so the naming points at formal verification of floating-point designs — but the notes stop short of saying so. The removals are worth reading too: flowmap is gone from synth and synth_ice40, abc loses its -fast option, and read_aiger loses -wideports. If your scripts pass any of those flags, this is a breaking release. GitHub
Differentiable power analysis, at a reported 1,002× over single-threaded CPU
DiffPower translates a netlist into a PDK-agnostic bytecode representation and computes analytical gradients through it by reverse-mode automatic differentiation, which makes switching power a quantity you can optimize directly rather than only measure. The speedup figure is against single-threaded CPU processing, so read it as GPU-versus-one-core rather than a like-for-like comparison. The work is Duke with Synopsys, which is worth noting — differentiable, PDK-agnostic infrastructure showing up in an EDA-vendor collaboration says something about where the commercial tooling expects to go. arXiv · SemiEngineering
AnalogSyn synthesizes multistage op-amp topologies, compensation included
Automated analog topology synthesis has a persistent abstraction problem: build at transistor level and you drown in structural detail, abstract too far and you lose the transistor behaviour that decides whether the circuit works. AnalogSyn targets multistage operational amplifiers specifically, where the compensation scheme drives most of the structural variation, and makes compensation a first-class part of the synthesis rather than something bolted on afterward. Analog remains the part of the flow least touched by automation, so work aimed squarely at it is worth noting. ACM
A benchmark asking whether LLMs can generate fast hardware, not just correct hardware
FinHardBench is 33 financial-computing tasks on FPGA, a domain where five to ten nanoseconds of latency is the entire point and designs churn as protocols and regulations change. The three experiments mirror a real iteration cycle: generate modules from specifications, tune system-level configurations, and iterate. Most LLM-for-RTL benchmarks stop at functional correctness, so a benchmark that treats latency as the objective is testing something the existing ones do not. arXiv
An argument that agents keep re-deriving what should be compiled once
Agents generating kernels for new accelerators work from architectural documentation and simulator feedback, and this paper's observation is that they reconstruct the same workload-invariant facts every single time — instruction behaviour, legality constraints, synchronization rules, memory protocols. The proposal is to compile those semantics once into a persistent symbolic artifact and leave the neural reasoning for what actually varies per workload. That is a claim about how to build agent systems generally, not just kernel generators. arXiv
Forbench uses symbolic simulation to make existing testbenches more formal
Simulation wins on deployability and loses on coverage: it explores a subset of traces and misses rare corner cases. Formal verification has the opposite profile, and scalability keeps it from displacing simulation on large designs. Forbench works the seam by applying symbolic simulation to testbenches that already exist, which is a more incremental path than asking a team to adopt a formal methodology outright. arXiv
Memory for all of 2027 is reportedly sold out
The claim circulating this week is that DRAM and HBM capacity for the entire 2027 calendar year has been booked, with Samsung's 4nm wafer capacity reported as fully booked through 2027 as well. This is a sharper version of the capacity story than the fab-buildout data points of a week ago — not "demand is absorbing capacity years forward" but "there is none left to buy for a specific year." Treat the specifics as reported rather than confirmed, but the direction has been consistent for months, and it sets the cost floor for anyone specifying memory into a design now. r/hardware · Samsung 4nm
A full-system processing-in-memory simulator covering 11 memory technologies
PIM has an obvious chicken-and-egg problem: the hardware is scarce, so almost all evaluation is simulated, so the simulator's fidelity decides what the field believes. PIMID, from RIKEN, Keio, Los Alamos and Oak Ridge, is a full-system simulator explicitly built for breadth across memory technologies rather than depth in one. Whether it becomes the common reference depends on adoption, but the diversity target is the right one for a field where the memory technology is the variable under study. SemiEngineering
A photonic MEMS switch that needs no process changes
The UC Berkeley result reports more than 30 dB extinction ratio and under 1.5 dB insertion loss from a silicon photonics MEMS optical switch built with a zero-change foundry-compatible process plus back-end-of-line post-processing. "Zero-change" is the load-bearing phrase — it means the foundry runs its existing process and the device comes from what happens afterward, which is a materially different access story than one requiring a custom flow. SemiEngineering
Also noted
- Samsung and SK Hynix are reportedly testing Chinese chip-making tools as a hedge against US policy risk — r/hardware
- LACE translates natural-language RISC-V instruction-extension intent into a two-level IR via an LLM multi-agent workflow — arXiv
- Apache TVM cut v0.26.0.rc0 — GitHub
- Tenstorrent moved on to tt-metal v0.76.0 release candidates — GitHub
- Fovea does wafer-scale design-space exploration with reticle compliance and wafer tiling as first-class constraints — arXiv
- LEAP models per-cycle toggle propagation self-supervised, for power analysis early enough to act on — arXiv
- Attention-based multi-scale modelling for dynamic IR drop analysis — ACM
- Two companion papers on microarchitectural policies: the limits of ML-learned ranking, and dynamic selection among policy stacks — limits · dynamic selection
- PICopilot generates photonic IC design scripts, targeting the GUI-to- script shift in PIC design — arXiv
- A decode-phase serving design that moves the KV cache out of GPU memory onto general-purpose processing-near-memory — arXiv
- Ternary LLMs get lookup-table attention with signed-digit K/V caches, so attention runs on the same machinery as the projections — arXiv
- A system-level argument that peak TOPS/W is the wrong lens for hybrid digital, analogue and neuromorphic computing — arXiv
- r/Semiconductors discussing third-party verification of SMIC 7nm at commercial scale — r/Semiconductors
- Chips and Cheese finds a loose thread in NVIDIA's Vera whitepaper — Chips and Cheese
- Non-linear function interpolation for LLMs via FPGA partial reconfiguration — arXiv
111 items considered: 39 arXiv · 39 Reddit · 17 RSS · 10 GitHub · 2 Hugging Face · 2 OpenAlex · 1 crates.io · 1 HN · 0 conferences · 0 PyPI. Weekly landscape sources (USPTO patents, SEC Form D) were not due this run. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.