What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
AMD bought Taalas, which etches model weights into silicon
Taalas, founded 2023 in Toronto, builds model-specific ICs: the weights live in a mask-ROM fabric on the die rather than in HBM, with an SRAM region for KV caches and fine-tuning adapters. Its HC1 test chip is reported at 16,960 tokens/second serving Llama 3.1 8B — vendor numbers, claimed as 48× Nvidia GPUs and 8.5× Cerebras — and the next part targets 20B parameters. AMD reportedly plans to pair the chips with its Helios racks, GPUs doing prompt processing and Taalas parts doing token generation. The obvious catch is baked in: a chip is locked to its model, and the mitigation on offer is that a re-spin only touches two metal layers. Whether hardwired models can track a field that ships new weights monthly is now AMD's problem to find out, at production scale. The Register · EE Times · HN · r/hardware
Jane Street published an ASIC reverse-engineering puzzle — GDS only
The firm designed a custom chip and released nothing but its GDS — the raw geometric layout — as a challenge: recover the netlist, work out what the chip does, extract an answer string. The suggested tools are KLayout and Magic, and a warm-up walks through a binary adder from Verilog to layout so newcomers can learn the mapping. Submissions close September 4. Layout-level literacy with open tools is usually a niche skill practiced inside foundry NDAs; a trading firm turning it into a public recruiting puzzle is a signal of where hardware talent is being hunted, and it hands the open-tool stack exactly the kind of approachable on-ramp it rarely gets. Jane Street blog · HN
Azure measured what agentic AI workflows actually do to datacenters
A production study at Microsoft Azure plus a controlled study of open-source frameworks, presented as the first architectural characterization of agentic workflows. The paper organizes agent workloads into a taxonomy and measures how their execution differs from the chat-style serving that current inference infrastructure was tuned for. Anyone sizing accelerators, memory, or interconnect for the next generation of datacenter silicon has been guessing at these numbers; production traces are the ground truth the guessing gets replaced with. arXiv
Coherence protocols for the CXL/CHI era, synthesized instead of hand-built
Processor design is converging on cache hierarchies that are heterogeneous, hierarchical, and scoped — cluster-level protocols stitched together under global ones like CXL or AMBA CHI. Hand-building these protocols is notoriously error-prone, and verification effort explodes with each level of nesting. This work synthesizes them automatically from the composition structure. Coherence bugs are among the most expensive class of silicon escapes, so moving protocol construction from artisanal to generated is the right direction even if the method only covers part of the space. arXiv
LLMs finding and fixing security bugs in Verilog, pre-tapeout
Hardware vulnerabilities differ from software ones in the way that matters most: after fabrication they are permanent. This work applies LLMs to detecting and repairing security vulnerabilities in Verilog designs while they are still editable. The detect-and-repair loop is the same shape the software-security world has been converging on; the pre-silicon deadline makes the hardware version higher-stakes and, if it works, higher-value. arXiv
PowerScope estimates power inside the clock cycle, with ML
Power delivery network design, voltage-droop analysis, and side-channel evaluation all need power estimates at sub-cycle resolution, and the standard answer — commercial post-layout gate-level power analysis — is slow enough that it gates how much of the design space gets examined. PowerScope trains ML models to produce intra-cycle estimates instead. Fast approximate power at fine time resolution is one of those capabilities that changes which analyses are affordable to run at all. arXiv
An open-source power measurement platform for silicon bring-up
Industrial semiconductor test equipment is expensive and hard to instrument, which keeps accurate power measurement out of reach for exactly the small teams and academic labs doing open silicon work. This paper presents an open-source platform for system-level power measurement and stress testing. Open test equipment lags open EDA by years; every piece that appears removes one more "and then you need the commercial lab" step from the open flow. arXiv
Also noted
- SemiEngineering's week in review: SK hynix's $38B new fabs, a $1.65T 2026 chip-revenue forecast, new US restrictions, and an NXP–Ambarella acquisition rumor — SemiEngineering
- GlobalFoundries' data-center growth as the case for a US photonics buildout — EE Times
- Chiplet architectures pitched as the practical path to scalable automotive compute — EE Times
- PLoRA serves 1000-plus LoRA adapters from a near-data-processing pooled-memory system — arXiv
- Kerckhoffs-compliant watermarking for physical-design IP, from placement through routing — arXiv
- A survey of hardware design and security in the chiplet-plus-LLM era — arXiv
- Zero-instruction sensor reads: specializing a five-stage soft RISC core around a self-balancing bicycle's control loop — arXiv
- EdgeXpert combines mixture-of-experts and speculative decoding for memory-efficient edge LLM inference — arXiv
- Design principles for heterogeneous DRAM-PIM-GPU systems, aimed at decode-phase LLM inference — arXiv
- Memory bottlenecks in quantum control systems, and architectures to break them — arXiv
- Microchip opened a PolarFire FPGA design contest — r/FPGA
- New crate: rustdv-gpi-sys, hand-written Rust FFI for the VPI simulator interface targeting Icarus Verilog — crates.io
- New crate: npnp, a pure-Rust LCEDA/EasyEDA downloader and Altium/KiCad library exporter — crates.io
- Compile-time vs. runtime FIR coefficients through the open-source Bambu HLS flow, with DSP inference falling out automatically — r/FPGA
112 items considered: 44 arXiv · 31 Reddit · 19 RSS · 10 GitHub · 3 Hugging Face · 2 HN · 2 crates.io · 1 OpenAlex · 0 conferences · 0 PyPI. Weekly landscape sources (USPTO patents, SEC Form D) were not due this run. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.