What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
nextpnr 0.11 lands, mostly as placer work
The place-and-route half of the open FPGA flow cut 0.11, and the changelog is almost entirely placement: placer-static gets robustness and quality-of-results improvements plus support for more architectures, and placer-heap gains a control-set-aware legalisation API currently used to speed up Xilinx placement. Vendor-specific work covers Gowin routing performance, ECP5 edge-clock placement, and more IOLOGIC primitives and DDR3 memory interfaces on Nexus. Releases will now be named after mountains. Placer quality is the specific thing that decides whether an open flow can hold timing on a real design, so unglamorous QoR work here is worth more than a feature list. GitHub
A tiny LLM reported at 21,000 tokens/second on a $250 FPGA board
A Show HN demo puts a small language model on a KV260 board, priced at $250 in the author's own framing, with a live demo attached and a claimed 21,000 tokens/second. The model is tiny and the number is the author's, not an independent measurement, so treat it as an existence proof rather than a benchmark. What makes it interesting is the shape: weights resident on-chip, no external memory in the loop, on hardware a hobbyist can actually buy. That is the same architectural bet the model-in-silicon startups are making, at four orders of magnitude less capital. mikeayles.com · HN
HLSmith gives an HLS agent the recipes instead of hoping it knows them
Frontier models can write C++ but lack the procedural knowledge to turn it into a fast FPGA accelerator — they pick poor architectures and apply hardware transformations inconsistently. HLSmith's answer is to stop treating that as a prompting problem: it encodes an expertise library of guarded transformation recipes with their prerequisites and their unsafe cases, drives agents through a staged synthesis / bottleneck-analysis / optimization loop modeled on how HLS experts actually work, then distills trajectories from commercial models into fine-tuning data for open-weight ones. Evaluated on PolyBench against ChatHLS. The interesting claim is structural — that the missing ingredient is codified engineering process, not model scale. arXiv
Fuzzing the synthesis tool, not the design
Most verification effort assumes the EDA tools are correct and hunts for bugs in the RTL. SynaSpace inverts that: it tunes the configuration of Verilog test generators to more effectively expose latent faults in logic synthesis itself, where a miscompile silently produces a netlist that does not match the source. Anyone leaning on an open synthesis flow inherits those bugs without a vendor to escalate to, which makes tool-directed fuzzing more valuable in open silicon than in the commercial world that mostly funds it. ACM
Capacitance extraction gets a variance-reduction trick
Floating random walk is the workhorse for parasitic capacitance extraction at modern densities, and being Monte Carlo, its runtime is set by the variance of what it samples. This work applies generalized antithetic sampling to cut that variance. Extraction sits in the inner loop of every sign-off iteration, so a constant-factor speedup there is felt across the whole flow rather than in one tool. ACM
Bug localization for RTL, learned from multiple feature views
Dynamic bug localization narrows a failing simulation to the lines responsible, which is the expensive part of debug once a test fails. This work combines multiple feature representations of the design under deep learning to do that ranking. Verification is where hardware schedules actually go, and localization is the step least helped by throwing more simulation at the problem. ACM
SKYLIGHT proposes a hundred-channel 3D photonic tensor core
Photonic compute keeps stalling on scalability and reliability rather than raw physics. SKYLIGHT co-designs topology and wavelength allocation for a 3D photonic in-memory tensor core aimed at real-time inference, claiming hundred-channel scale. It is an architecture paper, not a chip, and the photonics field has a long record of promising architectures that meet the process on the way down. Worth reading for the co-design method more than the projected numbers. ACM
FAPlace optimizes chiplet placement and interposer footprint together
2.5D integration usually places chiplets first and sizes the interposer around the result, which leaves silicon area on the table because the interposer is expensive and its footprint is set by the worst placement decision. FAPlace jointly optimizes both in a mask-guided sequential framework. As chiplet counts rise, packaging cost stops being a downstream consequence of the floorplan and becomes a term in it. SemiEngineering
Also noted
- Magic tagged 8.3.681, continuing its steady patch cadence — GitHub
- openRuyi 2026.07 released, a RISC-V distribution effort — r/RISCV
- Project Oberon ported to run on RISC-V instead of Wirth's original RISC-5 — HN
- A retention-aware RISC-V ISA extension and FPGA memory controller that trade MLC non-volatile memory write latency against retention time — arXiv
- G-Power builds architecture-level GPU power models by transferring knowledge from already-characterized GPUs — arXiv
- Dual-view memory for NPU-PIM systems, dropping the assumption that each tensor is bound to a fixed execution device — arXiv
- QCORE, a QPU-side real-time control architecture with shared AI acceleration for closed-loop calibration and error correction — arXiv
- Power switch network optimization via ML prediction of inrush current and wakeup latency — ACM
- SAI virtualizes GPU shared memory into underused L2 to lift thread-level parallelism — ACM
- Testing chiplet interconnects by bypassing the isolation logic that structural test normally relies on — ACM
- A hardware-aware look at where CMOS Ising machines fit in a robotics planning stack — arXiv
- FuriosaAI to supply 8,800 AI chips for a Stockholm data center — r/hardware
- Hot Chips 2026 proceedings expected in about 13 days — Hot Chips
- Rust SIMD on the GPU — HN
- Someone is building a hardware/software design sandbox around a gate-level simulator — r/FPGA
85 items considered: 32 Reddit · 14 RSS · 10 arXiv · 8 GitHub · 8 OpenAlex · 6 HN · 5 Hugging Face · 1 conferences · 1 crates.io · 0 PyPI. Weekly landscape sources (USPTO patents, SEC Form D) were not due this run. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.