What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Nvidia is reportedly trimming Rubin Ultra memory as the shortage reaches the flagship roadmap
Tom's Hardware reports Nvidia is testing lower-memory configurations of Rubin Ultra — as little as 192 GB, with a step back from HBM4E to HBM4 — in response to the memory supply crunch. This is the story from last week's "memory for 2027 is sold out" item arriving at its logical destination: the shortage is no longer a procurement problem downstream of the roadmap, it is reshaping the top of the roadmap itself. When the binding constraint on an accelerator is DRAM allocation rather than compute, every architecture that spends memory to buy throughput gets re-examined. Tom's Hardware · r/hardware
ArchAgent v2 scales agentic microarchitecture search to multi-level prefetching
The original ArchAgent discovered single-level cache replacement policies in competition settings. Version 2 takes on multi-level data prefetching — a much larger design space with strict hardware budgets and long simulation loops — using the Data Prefetching Championship as the test bench. The pattern to watch is agents graduating from tuning a policy at one point in the memory hierarchy to searching across coupled levels, which is where human architects spend their judgment. Competition benchmarks are not shipping silicon, but they are the field's agreed scoreboard, which makes claims here checkable. arXiv
A KiCad MCP server built on the official KiCad 10 Python API
A new PyPI package, kicad-mcp-kipy, exposes KiCad 10 to agents over MCP using kipy, the project's official Python API. It is brand new and small, but the ingredients matter: KiCad 10 shipping a supported API and someone immediately wiring it to the agent protocol means LLM tooling for the mainstream open ECAD suite no longer has to scrape project files or drive the GUI. Board design is becoming an agent surface through the front door. PyPI
ARMOR attacks RTL simulation's front-end bottleneck with node compression
High-performance RTL simulators lower each node of the design graph into its own instruction sequence, which enables compiler optimization but bloats the code footprint far past instruction cache capacity — the authors profile over half of pipeline stalls to the CPU front-end. ARMOR compresses nodes to keep the unrolled graph's benefits while fitting the cache. Simulation throughput is the tax every verification cycle pays, so structural wins in simulator codegen compound across a whole project in a way that buying more machines does not. arXiv
FSGen generates fused, sparse LLM accelerators with an early power model
FSGen is an agile generator for attention-based LLM accelerators that supports fused-operator dataflows and sparsity, paired with an early-stage PPA estimator so design-space exploration happens before RTL exists. The generator-plus-estimator shape is the interesting part: it moves the accelerator design loop up to the specification level, where an agent or a human can sweep a diverse design space cheaply and only commit the winners to implementation. arXiv
C2C-Explorer treats chip-to-chip interconnect as a searchable design space
Scaling LLMs across multiple processor chips makes chip-to-chip communication a first-order design variable, and C2C-Explorer builds the missing exploration loop: an LLM-workload-driven traffic generator, a scalable interconnect simulator, and Bayesian search over the exponentially large architecture space. Papers like this are the codesign toolchain assembling itself in public — the interconnect between dies is getting the same DSE treatment the dies themselves already have. arXiv
Also noted
- Apache TVM v0.26.0 went final, following the release candidate noted last week — GitHub
- Tenstorrent's tt-metal v0.76.0 also went final after its RC run — GitHub
- CIRCT cut firtool-1.155.0 — aggregate constant folds, more LLHD loop shapes, ImportVerilog work — GitHub
- SiliconCompiler 0.38.3 adds a beta of hierarchy handling for parameterized modules — GitHub
- Project Oberon — Wirth's complete system — ported to run on RISC-V instead of its original RISC-5 core — GitHub · HN
- antirez published h3.c, hand-written native MiniMax-H3 inference for Apple Silicon — GitHub · HN
- Llama.cpp reportedly runs 11–16× faster in macOS VMs with GPU passthrough than expected — trycua · HN
- SLAC: an access-driven CPU-to-GPU side channel through the shared system-level cache on Apple Silicon — arXiv
- ReVolt mitigates voltage droop in 2.5D PIM chiplet systems with an LSTM surrogate of the power delivery network — arXiv
- Eco-SoC proposes dynamic precision scaling for energy-proportional edge AI silicon — arXiv
- A hybrid ASIC-FPAA fabric that obfuscates analog circuit topology in a programmable transistor-pair array — arXiv
- New crate: forj, a suite of Rust tools for working with (System)Verilog designs — crates.io
- South Korea is launching a $3.5B chip fund and consulting the US on a swift military relocation to clear its Gwangju chip belt — r/hardware · r/hardware
- Chips and Cheese talks with Synopsys about the physics of chip design at DAC 2026 — Chips and Cheese
- A from-scratch CNN accelerator on a $25 Tang Nano 20K FPGA, posted as a build photo with 149 upvotes and counting — r/FPGA
Landscape watch
- Form D: NonPublic Semiconductor Fund II, a Series of NonPublic Master, LP (Florida; matched "semiconductor") — SEC EDGAR
94 items considered: 38 Reddit · 19 arXiv · 14 RSS · 9 GitHub · 7 OpenAlex · 4 HN · 1 PyPI · 1 crates.io · 1 SEC Form D · 0 conferences · 0 Hugging Face. One adapter failure: the weekly USPTO patent scan needs USPTO_ODP_API_KEY provisioned and was skipped. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.