What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Chisel starts deprecating implicit truncation
Chisel v7.14.0 begins the deprecation of implicit truncation, and the paired firtool release (1.155.0) now warns on any implicitly truncated value. The prescribed fixes are explicit: repair your widths, extract bits, use .squeeze, or reach for the new truncating connection operator :%=. Silent width truncation is a classic source of RTL bugs that simulate fine and fail in review, so the mainstream open HDL making it loud is a maturity move — at the cost of a migration tax on every design that has been leaning on the old behavior, which is exactly why the deprecation is staged through warnings first. GitHub
An audit finds INT8 quietly withdrawn across the Blackwell Ultra stack
Nvidia's published specs give the B300 roughly a 30:1 dense-compute ratio between FP8 and INT8 tensor-core throughput, where H200 and B200 both provide 1:1. This paper traces what that means in practice through four layers: the PTX ISA never exposes the fifth-generation tensor-core integer path, CUTLASS follows, and the withdrawal propagates into vLLM and SGLang. For anyone with a W8A8 quantization pipeline, the practical reading is that the INT8 path is being retired out from under it. The method is as notable as the finding: spec sheets are marketing documents, and this is what checking one against the ISA and the kernel libraries actually looks like. arXiv
A full-stack result says faster flash can make LLM serving worse
High-Bandwidth Flash stacks NAND behind a wide package-local interface — flash capacity at much better read latency and bandwidth than an SSD. The tempting move is to keep an SSD-style KV-offloading stack and swap the backing tier. This characterization tests that with four two-hour production traces, five models, and H100/B200 profiles, and finds serving gets worse, not better: a faster far tier only helps when read I/O is actually the serving bottleneck. It is a clean example of why memory-tier intuition does not survive contact with the full stack, published just as HBF is being pitched as HBM relief. arXiv
CHORUS post-trains complementary experts for testbench stimulus
High-coverage stimulus generation is one of the tasks where verification effort actually goes, and CHORUS is a post-training framework that pushes past the standard supervised-fine-tuning-then-RL pipeline for it. The core observation is that staged fine-tuning produces behaviorally distinct models, and coverage is exactly the kind of objective where complementary specialists beat one generalist. Executable feedback — coverage numbers from a simulator — gives the training loop a signal that textual imitation cannot, which is the same lesson software code generation already learned. arXiv
The stalls you measure separately don't add up separately
Branch mispredictions and cache misses are usually studied as independent bottlenecks — perfect-branch and perfect-cache speedups reported as isolated ceilings, their product treated as the joint limit. This paper shows that in irregular workloads the two interact in the same hot loops: faster memory reaches mispredicted branches sooner, and better prediction leaves more long-latency loads exposed in the window. The authors name the interaction symbiotic stall latency and quantify it. Anyone justifying a prefetcher or predictor investment from idealized isolated studies is doing roadmap math this result says is wrong. arXiv
Optics-for-AI-scaling coverage converges, and turns geopolitical
Not one event but a drumbeat: in a single day SemiconductorEngineering ran pieces on copper losing its grip on AI scaling as clusters push past rack-scale, what it takes to deploy co-packaged optics in production, and linear optics that move signal processing back onto the host SerDes. Meanwhile Tom's Hardware reports that photonics has landed in the crosshairs of the upcoming US-China summit. The interconnect between racks is having the moment the interconnect between dies had last year — and when trade policy starts naming a technology, the access questions that reshaped the memory market tend to follow. SemiEngineering — copper · SemiEngineering — CPO · SemiEngineering — linear optics · Tom's Hardware · r/hardware
FQTree takes boosted decision trees from quantization-aware training to hardware
Boosted decision trees still rule latency-critical inference — trigger systems, finance — and their hardware deployments mostly rely on uniform or hand-tuned fixed-point formats. FQTree does fine-grained quantization-aware training with a hardware-oriented leaf-value scheme, and the companion QXGB framework generates the hardware automatically. The code is public. End-to-end pipelines from training decision to generated RTL are what turn a paper into a tool people actually run. arXiv · GitHub
Also noted
- SiliconCompiler 0.38.4 adds PNRFlow, a place-and-route-only flow that ASICFlow is now assembled from — GitHub
- nextpnr 0.11.1 is a point release fixing the WASM build broken in 0.11 — GitHub
- Tenstorrent posted GCC compiler patches for its Ascalon XG RISC-V core — Phoronix · r/RISCV
- WCH's CH32V407/467 RISC-V MCUs integrate a Fast Ethernet MAC+PHY, a 480 Mbps USB 2.0 PHY, and up to 8 MB on-chip PSRAM — CNX Software · r/RISCV
- Samsung Foundry's updated roadmap moves 1.4nm to 2029, with high-NA EUV slated for 1nm-class nodes in 2030 and beyond — Tom's Hardware · r/hardware
- New crate: xlsynth-vast, a Rust-native Verilog and SystemVerilog AST and emitter — crates.io
- New project: edge-cores, pitching the shortest path from PyTorch to custom ASICs — GitHub
- APEX prefetches experts predictively for memory-constrained edge MoE inference — arXiv
- NITRO does in-storage computing in 3D NAND with a dataflow for the intermediate activations — arXiv
- Uni-SFU co-designs universal special-function units via mixed-degree piecewise approximation — arXiv
- Charge-CIM attacks analog compute-in-memory's ADC wall with reconfigurable switched capacitors — arXiv
- Probabilistic saturating counters for branch predictors, analyzed with formal differential-privacy guarantees rather than empirically — arXiv
- Scheduling transversal CNOTs so the classical decoder keeps up in fault-tolerant quantum computation — arXiv
- A unifying adjoint-method theory of when a physical computing system can compute its own training gradients — arXiv
- SemiconductorEngineering on what "self-verifying" should mean in agentic EDA workflows — SemiEngineering
95 items considered: 36 Reddit · 27 arXiv · 18 RSS · 11 GitHub · 2 crates.io · 1 HN · 0 conferences · 0 Hugging Face · 0 OpenAlex · 0 PyPI. Weekly landscape sources (USPTO patents, SEC Form D) were not due this run. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.