What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
A contract-grade verifier calls the bluff on LLM kernel correctness rates
Systems that generate GPU kernels with language models report high correctness rates, and this paper is blunt about where those rates come from: a single loose test that runs the kernel on a few random inputs at one fixed shape and accepts anything close to a reference. A kernel can pass that and still return an ordinary number where the true answer is a NaN, or differ from run to run. The authors build a contract-grade verifier to close those holes, and ship a native Blackwell backward pass for the gated-linear-recurrence family alongside it. As agent-generated kernels move toward production use, the verifier is the artifact that decides whether anyone's correctness claims mean anything. arXiv
GateTruth asks whether RTL benchmarks could even catch a wrong design
Benchmarks for LLM RTL generation have proliferated, and by this paper's count none reports applying mutation testing — the standard hardware-verification technique for measuring testbench quality — to its own testbenches. A testbench that never fails is not evidence of a correct design; it may simply never stimulate the bug. GateTruth injects mutations into benchmark designs and measures what the testbenches actually detect. Every RTL-generation leaderboard number inherits the quality of the harness underneath it, so auditing the harnesses is overdue work. arXiv
Spec-driven RTL evolution, with proofs carrying the update
Hardware development is evolutionary: major revisions start by changing intended behavior and then updating a previously validated implementation, not by regenerating RTL from scratch. Most LLM-for- hardware research still frames the task as prompt-to-RTL generation, and this work targets the gap — the specification becomes an executable contract that gets refined, and proof guidance drives the RTL update so the trusted parts of a legacy design stay trusted. Semantic version evolution is where production teams actually live, so tooling aimed at it is aimed at the right problem. arXiv
SynAct puts a reasoning-acting agent inside synthesis tuning
Logic synthesis results are highly sensitive to the choice and order of optimization commands, which makes tuning high-dimensional and expensive. Existing automation does black-box search over fixed action spaces; SynAct instead runs a reasoning-acting loop that can explain its decisions and adapt its strategy per design. Synthesis tuning is a bounded loop with a numeric scoreboard, which is exactly the shape of problem agents are currently good at — the open question, as always, is whether the gains survive designs the agent hasn't seen. arXiv
Agents put to work explaining why prefetchers fail
Prefetcher design is trace archaeology: architects inspect execution and memory-access traces, spot patterns, translate them into online hardware heuristics, and hope simulation agrees. No human systematically reads billion-instruction traces across diverse workloads, so this paper hands the inspection to agents and asks them to answer why prefetchers miss. Where ArchAgent, noted earlier this week, put agents to work searching the prefetching policy space, this work points them at the diagnosis step instead — the two halves of the loop are being automated from both ends. arXiv
Meanwhile, r/chipdesign says AI has made designers' lives harder
The counterweight to all of the above: one of the week's most-upvoted r/chipdesign threads, cross-posted to r/Semiconductors, is titled "AI has made the lives of chip designers harder, not easier." Practitioner sentiment is a datapoint the paper cluster does not capture, and the gap between what the research claims and what working designers experience is itself information. Worth reading the comments before assuming the tools are landing. r/chipdesign · r/Semiconductors
Also noted
- SemiEngineering's week in review: Lam and ASE expansions, a CPO system-architecture initiative, patent suits, and Nvidia's new plan — SemiEngineering
- The 1-megawatt rack debate: cram more compute per rack, or rethink the architecture — SemiEngineering
- Chips Act 2.0, part 1: an analysis of Europe's second semiconductor push — eeNews Europe · r/Semiconductors
- The LLM-EDA group published Edathon, a new model on Hugging Face — no card details yet — Hugging Face
- Dryas, a reprogrammable engine for tracing and analyzing high-speed interconnect protocols on FPGA — arXiv
- YAVIN extends trusted execution across processors, memory, and accelerators for secure edge processing-in-memory — arXiv
- ROLoad-PMP secures sensitive operations for kernels and bare-metal firmware with RISC-V physical memory protection — arXiv
- Lonic co-designs fully local online SNN training with INT4 precision down to real-device efficiency — arXiv
- The other side of Wednesday's HBF result: a report on where High-Bandwidth Flash could fit in LLM serving without undermining compute-die bandwidth expectations — arXiv
- Rivet, a Rust RTOS with a RISC-V port, preemptive scheduling, and SMP support — r/RISCV
- AdaptCore does adaptive matrix multiplication for dynamic tensor shapes on Ascend NPUs, where GPU-centric optimizations don't transfer — arXiv
- EU GPU prices are up roughly 19% in a month, per a tracker following 176 models across retailers daily — r/hardware
- Katie Schuman on why neuromorphic computing needs HPC engineers, compilers, and shared hardware access more than novel chips — EE Times
- TechTechPotato interviews Sameer Wasson on AI flipping chip design upside down — YouTube
- ReDON, a recurrent diffractive optical neural processor with reconfigurable self-modulated nonlinearity — ACM
110 items considered: 41 arXiv · 36 Reddit · 20 RSS · 10 GitHub · 1 HN · 1 Hugging Face · 1 OpenAlex · 0 conferences · 0 crates.io · 0 PyPI. Weekly landscape sources (USPTO patents, SEC Form D) were not due this run. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.