What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
A growth-theory paper puts chip design at the hinge of the explosive-growth question
NBER working paper w35155 — Davidson, Halperin, Houlden, and Korinek, "When Does Automating AI Research Produce Explosive Growth?" — builds a semi-endogenous growth model over an innovation network and asks what automating R&D actually does to output. The headline result: automating software research alone does not produce explosive growth in their model; the bottleneck just moves. Add modest automation of adjacent sectors — chip design first among them — and the feedback loop can close, with their calibration putting a growth singularity within roughly six years of full software-research automation plus about 5% automation elsewhere. The usual caveats apply with force: this is a calibrated model, not a forecast, and the parameter choices are contested — historical returns to chip-design R&D may over-credit cognition against fab capex. What the paper contributes is the network framing itself: which sectors' automation compounds, and chip design sitting where the model says the loop closes. NBER
An FPGA inference chip runs a real LLM layer in RTL, bit-exact
SigmanticAI's apex-inference-chip implements one transformer decoder layer of Qwen2.5-0.5B in RTL on an FPGA, with the repository claiming every silicon value bit-exact against the reference — and it collected over 500 GitHub stars almost immediately. One layer of a 0.5B model is an existence proof, not a product, but the bit-exact framing is the interesting part: it treats numerical equivalence with the software model as the verification contract, which is exactly the discipline the LLM-on-FPGA demos to date have skipped. It joins a lengthening line of weights-in-fabric experiments — the KV260 demo noted last week made the capital-cost version of this argument. GitHub
Alibaba's XuanTie C950 reported running a 27B Qwen model natively
A widely-shared report says Alibaba's XuanTie C950 — a TSMC-built 5nm RISC-V chip — now runs the Qwen-3.8 27B model natively. The sourcing is a news aggregator and the engineering details are thin, so hold the specifics loosely. The direction is the story: a top-tier RISC-V design running a frontier-lab-adjacent model from the same company is vertical integration from ISA to model weights, and it lands while the Grinberg ISA debate covered Sunday is still arguing about what RISC-V is for. Alibaba's answer appears to be: for this. wccftech · r/RISCV
λλ: a programming language for silicon photonics
An ACM paper presenting λλ, a programming language for silicon photonics, reached the Hacker News front page. Photonic design today happens at the component level, closer to analog layout than to software; a language-level treatment is the hardware/software boundary forming in a domain that has mostly lacked one. Last week's brief tracked the optics-for-AI-scaling drumbeat on the hardware side — this is the first programming-languages entry in that story to get broad attention, and worth reading for the abstractions it chooses even if photonic compute itself stays perpetually early. ACM · HN
GoalEvolve points program evolution at physical design, with goals instead of stage metrics
Physical design algorithms live inside tightly coupled multi-stage flows, where a stage-local gain can vanish or turn into downstream degradation — the same disease the PPAPlace benchmarking covered Sunday diagnosed in placement objectives. GoalEvolve argues existing program-evolution frameworks inherit that disease by evolving against stage-local or undifferentiated multi-metric feedback, and proposes goal-driven evolution instead: identify which unmet end requirement should steer the next iteration of the algorithm. Evolving the algorithms themselves, scored against flow-level goals, is a plausible next rung for AI-in-EDA above tuning tool settings. arXiv
NeuroAbs mixes neural guidance into RTL abstraction for property checking
Formal property checking on complex RTL lives or dies by abstraction — reduce the design enough to make the proof tractable without abstracting away the property. Choosing those abstractions well is expert work, and NeuroAbs frames it as a neuro-symbolic problem: neural components guide the abstraction while the symbolic machinery keeps the result sound for the checker. Verification is where formal effort actually bottlenecks in practice, so automation aimed at the abstraction-selection step is aimed at the expensive part rather than the already-automated one. arXiv
Cerebras overclocks the WSE-3 rather than wait for a new wafer
The Next Platform reports Cerebras's new CS-4 "Nexus" ships an overclocked WSE-3 wafer-scale engine to raise inference throughput — more oomph from the same silicon rather than a new generation. Inference demand is doing to wafer-scale what it has already done to every other accelerator roadmap: the pressure to ship throughput now beats the pressure to ship the next architecture, and thermal/yield headroom on a whole wafer is a knob most vendors don't have. A vendor report, not a benchmark; the interesting numbers will be sustained-throughput ones. The Next Platform · r/hardware
Also noted
- CIRCT cut firtool-1.156.0 — clocked LTL atom lowering, an AXI4 burst_set attribute, and BMC counterexample traces printed from satisfying Z3 models — GitHub
- Tenstorrent's tt-metal v0.77.0 is out, two release candidates after v0.76.0 went final last week — GitHub
- SiliconCompiler 0.38.5 adds die/core outline setters and two new demo targets — GitHub
- Clean-room microbenchmarks characterize the concurrency response of plain global loads on three H100 dies — arXiv
- Congestion-aware NoC placement and packet routing for the CAD flows of NoC-enhanced FPGAs — arXiv
- TRACE, a symbolic-computer-algebra engine for formal verification of arithmetic circuits — arXiv
- Renesis synthesizes verified, technology-mapped adiabatic (energy-recovery) circuits from ordinary irreversible netlists — arXiv
- DTX, a throughput-first training accelerator built so no reduction anywhere serializes through a single FP32 adder — arXiv
- Dynamic slack-aware clocking recovers timing margin in near-threshold TPUs — ACM
- ETHEREAL, a 25.6-µs/inference event-driven graph-neural-network processor for high-resolution edge vision — arXiv
- Etched, the $21B inference-ASIC startup, is reportedly hiring heavily from Nvidia — WSJ · r/hardware
- Samsung has reportedly raised chipmaking prices by up to 15% on the demand spike — Reuters · r/hardware
- MICRO 2026 program expected in about 13 days — MICRO
- r/chipdesign is venting about em dashes and emojis showing up in reports and code — the AI-tells complaint, from the practitioner side — r/chipdesign
- SemiEngineering on heterogeneous clusters: the future of AI compute won't run on one kind of chip — SemiEngineering
87 items considered: 39 Reddit · 22 arXiv · 15 RSS · 6 GitHub · 2 HN · 1 conferences · 1 crates.io · 1 OpenAlex · 0 Hugging Face · 0 PyPI — plus one editor-pinned paper (NBER w35155) predating its feed's fetch window. Weekly landscape sources (USPTO patents, SEC Form D) ran this week and matched nothing. No adapter failures. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.