What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Martin Fink's Ferrite Engineering opens a four-tool EDA beta, with Apache 2.0 promised after it
Ferrite Engineering — a new RISC-V International member org founded by Martin Fink — has EDACrux in public beta: WaveCrux (waveform viewer for VCD, FST, GHW), NetCrux (RTL schematic browser), LintCrux (lint dashboard), and SimCrux (regression manager), sharing a workspace and cross-probing between each other. The beta runs free with Pro and Enterprise features unlocked through early October; Ferrite says each tool's source, tests, build scripts, and waveform engine will be released under Apache 2.0 once beta ends, with a paid Pro tier for depth and speed. Read the license claim as a promise, not a fact: the four public GitHub repos today hold issue trackers and test fixtures and say plainly "No application source" — the SimCrux and LintCrux ones went up overnight. The pitch is worth watching regardless, because it is the one the open-EDA world keeps not getting: take what the community built and put integration and a modern UI on it, priced for people who can't expense a Verdi seat. RISC-V International · GitHub
TSMC reported finished with 1.6nm, mass production slated for Q4
Korea's Seoul Economic Daily reports TSMC has completed development of a 1.6nm-class process and expects volume production in the fourth quarter, a report that ran to 300 points on r/hardware. Single-outlet foundry roadmap reporting deserves the usual discount, and "developed" is doing work in that sentence — a completed process is not a qualified PDK in customers' hands. The reason it matters here is what the node cadence does downstream: another full node means another round of design-rule churn, another set of tools that have to be requalified, and a widening gap between what a leading-edge flow costs and what anyone outside the top handful of customers can reach. Seoul Economic Daily · r/hardware
An open RISC-V trace encoder that speaks both standard protocols
RISC-V standardizes two processor-trace formats, N-Trace and E-Trace, and CTTE is an open SystemVerilog encoder with a protocol-agnostic front end and selectable back ends for either. The authors claim that as of August 2026 no publicly available synthesizable N-Trace encoder had been reported, and no published encoder carried both back ends behind one front end. They integrated it with six RISC-V cores from five suppliers, booted Linux including a two-hart SMP system, and measured trace cost swinging from 0.21 to 4.90 bits per retired instruction on identical hardware depending only on workload — a useful number for anyone sizing a trace buffer. Debug infrastructure is the unglamorous half of open silicon and the half that decides whether a core is usable by anyone but its authors. arXiv
Assertion generation gets a formal loop instead of one LLM shot
NeuroAssertion attacks the failure mode that makes mined assertions untrustworthy: random or limited traces never reach the hard control-flow corners, and one-shot generation tells you nothing about what is still uncovered. It converts hard-to-reach conditions into formal reachability objectives, model-checks its way to behaviorally diverse traces, mines assertions from those with syntax-guided synthesis, then refines under verification feedback — one LLM proposes candidates for uncovered regions, and when a candidate fails formal checking a second LLM writes a repair grammar that constrains the symbolic re-synthesis. Reported results are roughly 2× the assertions at roughly 2× the coverage. The structure is the interesting part: the LLM never gets the last word, the checker does. arXiv
Ampere publishes how it actually verifies performance, across four core generations
Pre-silicon performance verification is usually described in vendor talks and never in enough detail to copy. This paper lays out the methodology used across four generations of the AmpereOne custom core: cycle-accurate correlation of RTL against a trace-driven performance model, data-driven workload curation, a high-frequency daily regression system, and a unified event-stream framework for analysis, with worked case studies on the branch prediction unit and the L2 prefetcher. The hierarchical strategy — correlate individual units before attempting full-core — is the sort of thing every team rediscovers privately. Worth reading as a description of the loop that AI-in-verification work keeps proposing to automate without describing first. arXiv
FIBER decouples GPU threads from register ownership
Tensor core throughput keeps rising while the pipeline around it stays awkward, and FIBER argues the bottlenecks are fixed parallelism and coarse-grained scheduling — both exposed by modern serving workloads that interleave non-GEMM work with GEMM. Its execution instance, the fiber, carries minimal control state and reaches an SM's registers through a shared view rather than owning private ones, which buys dynamic parallelism scaling, register-level dataflow scheduling, and another route for matrix operand supply. The authors extend ISA, microarchitecture, and compiler together and report 2.25× end-to-end on Ampere for mixed-precision LLM serving. It's a simulated architecture proposal, not silicon, but it is a proposal about the SIMT model itself rather than another accelerator bolted alongside it. arXiv
HYDRA searches chiplet composition and runtime policy together
Hybrid Transformer-Mamba models make serving harder to accelerate because the compute and communication patterns stop being uniform. HYDRA treats that as a joint design-space problem over chiplet composition, placement, inter-chiplet bandwidth, dynamic batching, and runtime scheduling, with a Markov-based estimator fast enough to keep multi-tenant runtime dynamics inside the search loop. Reported gains are 1.55× throughput and 43.7% lower time-to-first-token on average, up to 2.3× throughput at the top end. The claim underneath the numbers is the one to note: separating architecture search from runtime policy search leaves most of the win on the table. arXiv
The WUNKUS detector: a fabricated 22FDX MIMO chip, and the die shot r/chipdesign actually liked
A 22FDX ASIC implementing what its authors call the first multi-subcarrier massive MU-MIMO-OFDM detector in the open literature: 8 users, 64 basestation antennas, 16 subcarriers in parallel, soft outputs from QPSK to 256-QAM, 1.3mm² of core cell area, 286mW, 7.3Gbps at 0.8V, and 39pJ/b. Exploiting beamspace sparsity and frequency-domain correlation buys up to 3× area and power reduction. It surfaced on r/chipdesign as a die photo with a cat hidden in it — 144 points, which on a sub that spends most of its week on career questions is what enthusiasm looks like. arXiv · r/chipdesign
Also noted
- GHDL's nightly channel is now building 7.0.0-dev across its gcc, mcode, llvm, and llvm-jit backends — GitHub
- IREE is four release candidates into 3.12.0 since Tuesday — GitHub
- New crate: celox, an HDL simulator written in Rust, published alongside its macro crate — crates.io
- New crate: bitloom-vlog, lowering a FrozenHir to Yosys-friendly Verilog — crates.io
- Predicting MBIST area and test time straight from RTL-level design parameters, skipping synthesis and pattern generation, at a claimed 90.7% and 96.8% accuracy within ±10% — arXiv
- A fast all-digital adaptive voltage-droop response circuit, validated on an IHP 130nm test chip rather than in simulation — arXiv
- HyperCut prices inter-layer schedules before solving the intra-layer problem, using a hypergraph cut to bound the cost — arXiv
- ODEONN, a modular digital ODE-solver architecture for oscillatory neural networks, with a sine approximation at half the hardware — arXiv
- APEX puts the PASC-IF conversion neuron into a dual-sparsity SNN inference accelerator as a combinational datapath — arXiv
- An exact multistate reliability framework for HBM systems where a service unit can deliver partial rather than zero bandwidth — arXiv
- ONEX decomposes 2D execution planning for qLDPC codes on neutral-atom arrays into 1D subproblems solved to optimal depth by SMT — arXiv
- r/Semiconductors is arguing about whether a large semiconductor company can be serious about AI adoption — r/Semiconductors
- Chipstrat's state of the union on near-package optics — the intermediate step between pluggables and co-packaged optics, and the vendor language shifting toward it — Chipstrat
- TechTechPotato's Silicon Grapevine special on the rise of autonomous chip design — YouTube
- SemiEngineering's week in review: a new Micron lab, chip and AI price jumps, multi-die monitoring, an interconnect RC bottleneck, an 18A win, and a CPO roadmap — SemiEngineering
100 items considered: 38 Reddit · 32 arXiv · 21 RSS · 5 GitHub · 3 crates.io · 1 HN · 0 conferences · 0 Hugging Face · 0 OpenAlex · 0 PyPI. GitHub discovery searches hit rate-limit 403s on the first pass and completed on an authenticated retry; no other adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) were not due this run. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.