What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
One researcher and an AI agent fleet tape out a RISC-V chip with no human-written RTL
In five weeks, on consumer AI subscriptions, one researcher directed a small fleet of AI agents from application code, through a verified compiler and executive, to a RISC-V processor taped out on a community silicon shuttle — no RTL written by a human, no proof passed through human review. The discipline (the author calls it the "Salt method") routes mathematical claims between agents as Lean 4 kernel-checked artifacts, with SAT-checked equivalence at the silicon boundary, so human attention goes to statements, designs, and rulings rather than proof review. The paper publishes the full accounting — theorem provenance, a pre-registered token meter, floor-bounded human time, and an error ledger running to catch #256 — against zero incorrect proofs reaching the record. Worth reading skeptically as a self-reported single case, but the methodology (a proof kernel no hallucinated proof can pass) is the interesting part regardless of who ran it. arXiv
The RISC-V instruction set manual heads toward ISO standardization
ISO/IEC has published DIS 26791-1, a draft international standard for the RISC-V instruction set manual, now open for ballot. An open ISA becoming an ISO standard changes who can specify it in a contract — government and safety-critical procurement processes that require an ISO reference gain one, which is a different kind of adoption lever than another core tapeout. ISO · r/RISCV
SiFive ships a RISC-V server platform aimed at the datacenter
BigSky SF-2U870 is SiFive's pitch for RISC-V in the datacenter rather than the embedded and mobile markets the ISA is best known in — a 2U server development platform, not a paper roadmap. Datacenter CPUs are where RISC-V has the least presence today, so a shipping platform matters more than another announcement of intent. SiFive · r/RISCV
Multi-die assemblies become the default below 2nm
Semiconductor Engineering's rundown makes the case that modular, multi-die construction has stopped being an option at the leading edge and become the normal way advanced designs get built, as monolithic scaling runs out of room. The piece is a trend synthesis rather than a single news event, but it's the context for every EDA and packaging story that follows — interposers, chiplet interconnect, and known-good-die testing all get harder to treat as niche once this is the default, not the exception. Semiconductor Engineering
A TMR study puts real RTL-to-GDSII numbers on radiation-hardened NoC routers
Most prior work on protecting network-on-chip routers against single-event effects targeted narrow, deeply pipelined designs; this study runs full RTL-to-GDSII physical design in TSMC 7nm on a 2-cycle, 512-bit-wide-link router — the wide, low-latency style now common in AI accelerator tiles — and fault-injects over a million single-event upsets and transients per experiment. Coarse-grained and state-only Triple Modular Redundancy both let failures through; full TMR eliminated every observed failure, at a standalone 7.04x area cost that the authors show gets substantially amortized once the router is integrated into a complete accelerator tile with its surrounding processors. Useful as a concrete cost number for anyone specifying reliability margins on physical-AI hardware meant for harsh environments. arXiv
GPU undervolting nudges adversarial robustness for free
Undervolting a GPU during training introduces bit-level faults that the authors treat as implicit regularization rather than noise to eliminate. Training LeNet, VGG-6, and MobileNetV3 on MNIST and CIFAR-10 under both standard and adversarial regimes, the undervolted models came out more robust to adversarial attacks than their nominal-voltage counterparts every time, while also cutting power — dynamic power scales with the square of supply voltage. No algorithm change required, which is the whole pitch: a hardware knob doing double duty as a training-time defense. arXiv
SPICE speculatively prefetches MoE experts across the PCIe bottleneck
When a Mixture-of-Experts model's parameters don't fit in GPU memory, inference latency ends up dominated by PCIe transfers pulling experts in from the host. SPICE pairs a lightweight draft model that predicts which experts will be needed with a confidence-aware fallback: low-confidence misses get approximated by low-rank surrogates of the resident shared expert, and only the genuinely uncertain residual work gets sent to the CPU to run asynchronously alongside the GPU. On DeepSeek-V2-Lite and Qwen2-57B-A14B across several GPU platforms, that combination gets up to 3.12x lower time-per-output-token with little quality loss — the argument being that offloading needs a policy for what to approximate, not just a better predictor. arXiv
Also noted
- Xiaomi's Xring O3, a 3nm SoC built with TSMC and aimed at the Xiaomi 18 Fold, drew a die-shot thread and three separate first-look/launch threads across r/chipdesign and r/hardware — r/chipdesign · r/hardware
- Bern2Edge distills a trained network into Bernstein-polynomial hardware representations, with both a LUT-based and a symbolic-rule deployment path, tested on AMD Xilinx KV260 and a low-power Spartan-7 FPGA — arXiv
- Chips and Cheese's Hot Chips 2026 writeup on High-Bandwidth Flash as a cheaper-than-DRAM capacity play for ML workloads — Chips and Cheese
- Chips and Cheese's Hot Chips 2026 writeup on Samsung fabricating HBM base dies on a logic node — Chips and Cheese · r/hardware
- ServeTheHome on d-Matrix's Raptor 3D-DRAM accelerator for generative inference at Hot Chips 2026 — ServeTheHome
- New project: brokenBench, SystemVerilog and UVM debugging exercises modeled on ziglings — GitHub
- New crate: opencascade-kicad-parser, a KiCad file parser for use with opencascade-rs — crates.io
- An FPGA learning platform passed 372 exercises with in-browser simulation and new learning paths — r/FPGA
- RISC-V Week 2026: a week-long challenge running only RISC-V hardware, no x86 or Arm — r/RISCV
- NVIDIA published a same-day cluster of Vera Rubin platform posts: Spectrum-X Ethernet scaling, DSX MaxLPS performance-per-watt, the Vera CPU for agentic fleets, and the Groq 3 LPX inference accelerator — NVIDIA
- DATE 2027's CFP deadline is 12 days out — DATE
- im2win extends its memory-efficient convolution scheme to half-precision tensor-core execution, up to 2.8x higher throughput than its own CUDA-core version — arXiv
- A zeroth-order fine-tuning architecture for spiking transformers on in-memory-compute accelerators avoids per-weight random-number-generator overhead by exploiting spike sparsity — arXiv
- r/RISCV is discussing a proposed RISC-V Vector Matrix Extension — r/RISCV
66 items considered: 35 Reddit · 15 RSS · 9 arXiv · 3 GitHub · 1 crates.io · 1 Hugging Face · 1 conferences · 1 HN · 0 PyPI · 0 OpenAlex. OpenAlex failed with an HTTP 504 this run; the weekly landscape sources (USPTO patents, SEC Form D) were not due. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.