What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
An AI system reports designing, verifying, and deploying a frontier accelerator in two weeks
Architect Labs' Redwood paper describes an end-to-end system that collapses the software-to-silicon stack into one optimization loop: from a high-level specification written by two human architects, it generated the performance model, RTL, UVM environments, formal proofs, firmware, and kernels in under two weeks with no human intervention below the spec, taking every block to 95% coverage through commercial EDA tools, a proprietary formal engine, and hardware-in-the-loop validation, and turning around spec changes in under 48 hours. What actually runs today is Redwood Nano, an FPGA variant serving multi-billion-parameter models like Llama and Qwen; the headline performance numbers are projections onto Samsung 8nm, not measured silicon. It is a self-reported vendor paper and unverifiable from outside, but as with Monday's agent-fleet tapeout, the verification harness — coverage gates, formal checks, hardware-in-the-loop — is the part worth reading regardless of how the claims age. arXiv
OpenAI shows first benchmarks for Jalapeño, its clean-sheet accelerator
At Hot Chips 2026, OpenAI's Richard Ho presented first benchmarks for Jalapeño and made the framing explicit: not a repurposed GPU but a general-purpose AI accelerator built from scratch for AI workloads. The significance is structural — a frontier model lab disclosing its own silicon architecture at Hot Chips moves the lab-designs-its-own-chips story from reporting to the technical record, and every merchant accelerator roadmap now has to price in its biggest customers becoming competitors. EE Times
Microsoft publishes the Maia 200 architecture
Microsoft's paper on Maia 200 puts numbers on its second-generation accelerator — 10,145 TFLOP/s FP4 and 5,072 TFLOP/s FP8 in a 750W TDP with 7 TB/s of HBM bandwidth — and names the architectural idea: software-defined dataflow engines that explicitly orchestrate specialized memories and data-movement engines, shifting the design center from thread-centric to data-movement-centric execution. Between this and Jalapeño, Hot Chips week's theme is hyperscalers and labs describing their in-house silicon in public detail rather than press releases. arXiv
Nvidia is looking at CUDA on RISC-V hosts
Chips and Cheese's Hot Chips writeup covers Nvidia's work toward supporting CUDA host code on RISC-V processors — with, as the author puts it, terms and conditions attached. If it lands, RISC-V CPUs could sit at the head of Nvidia accelerator systems, which is a different order of adoption than another embedded design win: the dominant accelerator ecosystem opening its host side to an open ISA. The r/RISCV and Hacker News threads read it the same way. Chips and Cheese · HN
An open compiler from ternary LLM weights to mask-programmed silicon on SKY130
Ankhdjet lowers a Hugging Face ternary checkpoint (BitNet b1.58 and kin) to a via-mask program of a fixed compute-in-ROM macro on the open SKY130 PDK, verified end to end with open tools — KLayout DRC zero, netgen LVS zero, clean timing — run twice with two different weight matrices through an identical flow in which only the mask differs. The macro has been submitted to a TinyTapeout/ChipFoundry shuttle with silicon expected in 2027. Hardwiring model weights into silicon has a commercial existence proof behind closed tooling; this is the claim that the idea can be reproduced by anyone, on an open PDK, with the whole flow inspectable. arXiv
A deployed Rowhammer defense in Azure's Cobalt 200 gets broken on paper
Microsoft's Sigries — the memory-controller Rowhammer mitigation shipped in the Azure Cobalt 200 SoC — combines an under-provisioned Misra-Gries tracker with a sampling fallback, and claimed the sampling-to-tracker transition was always safe. This analysis shows that transition is also attackable: a round-robin attack across sub-banks drives mean-time-to-failure down to about one second, eight orders of magnitude below baseline sampling defenses. The authors' FiRM co-designs the two modes so the system stays secure during transitions, replacing the CAM tracker with SRAM filters. Whatever FiRM's fate, a production defense lasting one paper cycle is the argument for publishing these designs before deploying them. arXiv
What actually runs on the Apple Neural Engine, measured
A measurement study asks what gets a language model onto the ANE and answers with counters rather than compiler intentions: placement is a property of how a computation is expressed, not what it computes — a fused RMSNorm is fully ANE-eligible while its arithmetically identical decomposition is CPU-only — and weight encoding gates the accelerator, with a conv-heavy fp16 model assigned entirely to the CPU while the same graph in int8 or 2-bit returns to ~83% engine residency and runs 1.8–2.2x faster. Decode cost tracks bytes streamed per token at a constant fraction of encoding width. NPU deployment runs on folklore; this is the rare paper that replaces some of it with measurements. arXiv
OSCAR: an open accelerator generator whose power model survived a tapeout
OSCAR takes hardware and workload specifications and produces both architecture-level power estimates and synthesizable Chisel/RTL for AI accelerators, covering dense, Transformer, Winograd, systolic, and reconfigurable architectures in one framework. The power model uses architectural-level toggling features to reach a reported 3.8% error against post-synthesis power, and the team taped out a chip from their design-space exploration whose power the model predicted with over 90% accuracy. Open accelerator generators exist; one whose early-stage power numbers are validated against silicon is rarer and more useful. ACM
Also noted
- KLayout shipped 0.30.11 and a 0.30.12 hotfix within the window — GitHub (0.30.11) · GitHub (0.30.12)
- Magic 8.3.682's changelog credits Claude Opus with investigating and fixing a plane-property read bug — an agent contribution landing in a 30-year-old open EDA tool's release notes — GitHub
- tinygrad 0.14.0: over 1,000 commits, RDNA3 kernels for Qwen 3.8 27B, tool-calling support, parallel kernel compilation by default — GitHub
- CIRCT cut firtool-1.157.0 — FIRRTL register time-zero initial values and ESI cosim build speedups — GitHub
- New Rust crate trio: Struo, a logic synthesis toolkit from Veryl to FPGA targets, with frontend and RTL layers published separately — crates.io
- Simthesizer argues LLM-serving simulators should be extended by a harnessed coding agent against a composable abstraction rather than rewritten per feature — arXiv
- A perspective paper sorts LLM-in-EDA systems into generator, agent, and orchestrator roles and argues the field's "syntax trap" comes from training models on plausible code rather than correct hardware — arXiv
- SemiEngineering on LLMs turning specs into formal properties — the answer is approaching yes, with caveats — SemiEngineering
- r/FPGA is asking who actually has access to AMD's Vivado AI Assistant, an MCP-based early-access feature in 2026.1 wired into VS Code and Copilot — r/FPGA
- FLINT proposes a workload-driven High-Bandwidth Flash substrate for capacity-scalable LLM inference — the HBF paper drumbeat continues — arXiv
- An open-source benchmark suite of 3D-IC testcases, with virtual chiplet models for compute, memory, I/O, analog, and substrate — arXiv
- C-PathGen parallelizes critical-path generation for static timing analysis, 6.8–10.3x faster than its predecessor with exact results — ACM
- Chips and Cheese's Hot Chips series continued: Fujitsu's Monaka CPU, Intel's Diamond Rapids, Wildcat Lake, and Crescent Island — Chips and Cheese
- A GAO report says CHIPS Act fabs are progressing while the act's R&D money sits mostly unused, per IEEE Spectrum — IEEE Spectrum
- SYNTLOG, a benchmark collection of 101 FSMs from tens to thousands of states, compared against Vivado at the synthesis level — arXiv
196 items considered: 62 RSS · 60 arXiv · 47 Reddit · 13 GitHub · 6 crates.io · 3 OpenAlex · 3 Hugging Face · 2 HN · 0 conferences · 0 PyPI. No adapter failures. The 2026-08-26 pulse-day session was interrupted before ranking, so this brief covers the full window since 2026-08-24, including that run's fetched items. The weekly landscape sources (USPTO patents, SEC Form D) ran 2026-08-26 and matched nothing. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.