What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Google's Marvell deal signals custom silicon spreading beyond the TPU
EE Times reports Google's expanded relationship with Marvell as a signal that specialization is moving past the compute die itself: memory, networking, storage, and data movement are now candidates for custom silicon too, not just the TPU. If hyperscaler custom-silicon programs start treating the whole system — not just the accelerator — as fair game for specialization, that reshapes what merchant silicon and EDA vendors are actually competing for. EE Times
SK hynix reported tapping Intel Foundry for next-gen HBM base die
A Korean trade-press report, surfaced via r/hardware, says SK hynix plans to use Intel Foundry to manufacture the base die for its next-generation HBM stacks. The base die is the logic layer under the DRAM stack, so this would be Intel Foundry landing a role inside a competitor's flagship memory product — a concrete foundry-access data point in a year when everyone is re-litigating who can fab what. Single-source and unconfirmed by Intel or SK hynix as of this writing. Herald Corp · r/hardware
DeepSeq3 cuts model-checking time by learning register-transfer structure
DeepSeq3 abstracts a circuit into two levels — flip-flop-partitioned combinational subgraphs and a higher-level graph of register-transfer state — and pretrains by predicting reachability between flip-flop states before applying a dual-GNN architecture on top. On the paper's benchmarks that state-centric view reduces bounded model checking time by 18% while preserving correctness guarantees, which is a specific, checkable claim rather than a general representation-learning pitch. arXiv
A benchmark paper tests whether RISC-V vector hardware is actually fast
"Great Expectations" runs standard HPC benchmarks (BLAS, FFTW, HPL, HPCG, STREAM, FMA) on every RVV 1.0-capable chip currently shipping — SiFive X280 (on Tenstorrent Blackhole), SpacemiT's K1 and K3, and T-Head's C920v2 — against Nvidia Grace as the ARM64 HPC baseline. The finding is unglamorous and useful: RVV 1.0 beats scalar execution by a wide margin, but hardware-specific implementation gaps still keep it short of being a drop-in HPC option. This is what "RISC-V is ready" claims look like once someone actually measures them. arXiv
An LLM framework picks FPGA-vs-CPU task splits and explains why
Gen-TAS grounds an LLM in task-graph analysis and retrieval over past implementations to recommend which parts of an application should run on the FPGA fabric versus the general-purpose processor in FPGA-GPP heterogeneous systems, producing multiple explainable strategies for different objectives (latency, power, resource use) rather than one black-box answer. On CNN and SDR workloads it reports up to 2.45x and 92.53x speedups over all-GPP baselines under latency-oriented settings, with a deterministic backend still doing the actual implementation. arXiv
A cycle-level GPU simulator checks out against real H100 silicon
Purdue researchers built a cycle-level simulation framework spanning Ampere, Hopper, and Blackwell GPU generations and validated it against physical hardware, reporting a 99% Pearson correlation with measured H100 behavior. Simulators for distributed, asynchronous GPU systems are common; ones that get checked against silicon and hold up are the part worth trusting when using the tool to explore next-generation designs. Semiconductor Engineering
Also noted
- cocotb 2.1.0 shipped — the Python HDL verification framework's latest point release — GitHub
- A survey frames the LLM-serving "memory wall" across GPUs, ASICs, FPGAs, processing-in-memory, and neuromorphic/photonic approaches, concluding the memory system — not arithmetic — is now the bottleneck that matters — arXiv
- ROBBIN: a Rowhammer-based backdoor injection attack that characterizes a target DRAM's bit-flip pattern and uses it to plant backdoors during inference — Semiconductor Engineering
- PPAPlace trains chip placement on differentiable post-route timing objectives instead of half-perimeter wirelength, after benchmarking showed near-zero correlation between the two — Semiconductor Engineering
- Georgia Tech and Synopsys demonstrate a monolithic-3D 6T SRAM at the 2nm node using BEOL pass-gates on an all-silicon nanosheet latch — Semiconductor Engineering
- Semiconductor Engineering argues optical integration is turning chiplet packaging into a full-system co-design problem, not a plug-in bandwidth upgrade — Semiconductor Engineering
- Chips and Cheese's Hot Chips 2026 series continued: an interview with IBM's Christian Zoellin and Christian Jacobi, Samsung/XCENA's near-memory CXL device, and Samsung's LPDDR5X processing-in-memory — IBM interview · XCENA/Samsung CXL · Samsung PIM
- Oxford researchers propose hardware-managed heterogeneous HBM/HBF for LLM inference, continuing the High-Bandwidth Flash drumbeat — Semiconductor Engineering
- IEEE Spectrum, via Tech Policy Press: the EU's AI buildout is driving chip demand its own semiconductor strategy can't meet — the bloc is tracking toward roughly 11.7% of global chip production against a 20%-by-2030 target — IEEE Spectrum
- A paper reframes neuromorphic hardware design around continuous, non-spiking neuron models, arguing multi-bit packet passing and higher-order solvers beat the usual spike-based approach on energy and delay — arXiv
- sdrtop: a new Rust terminal monitor for HackRF One and RTL-SDR with live spectrum and waterfall views — crates.io
- Nvidia announced the Jetson Orin Nano 2, an entry-level edge board on Ampere silicon — r/hardware
- CP/M Neo, a CP/M-inspired operating system for RV32, is making the rounds in the RISC-V hobbyist community — r/RISCV
80 items considered: 31 RSS · 26 Reddit · 8 arXiv · 7 Hugging Face · 6 GitHub · 1 crates.io · 1 HN · 0 conferences · 0 OpenAlex · 0 PyPI. One RSS adapter failed (bunnie's blog). The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-08-26 and are not due again until 2026-09-02. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.