What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
An open, agent-first database packages analog IC designs as reusable, resimulatable objects
Analog design is hard to share: foundry NDAs restrict the process details a design depends on, and the testbenches behind published results are rarely released. analog-db packages each design as a process-neutral topology, reusable testbenches, and a machine-readable datasheet under one schema, with functional sub-blocks and device sizes exposed as named parameters an AI agent can discover and retarget. Across a 23-circuit regulator corpus imported from three open PDKs, 17 of 23 imported sizings failed their testbenches and were closed by an automated gm/ID sizing loop; in a case study, a coding agent working from the released artifacts sized a chopper instrumentation amplifier's op-amp cores and located four hand-entry defects plus a missing common-mode feedback loop that a sizing-only baseline didn't catch. arXiv
SiliconCompiler adds a logical-equivalence-check flow and an ML-to-ASIC front end
The open, Python-driven ASIC/FPGA build system's 0.38.6 release adds LECFlow — combinational, sequential, and k-induction equivalence checks — and a SODA Synthesizer front end that takes an MLIR-represented ML model through soda-opt and Bambu into the normal ASIC flow, with elaboration, synthesis, and ASIC stages now taking a front end instead of a fixed language. The same release adds job cancellation and ownership checks to the remote/Slurm scheduler path. Concrete progress toward more of the design flow — model-to-silicon, not just RTL-to-GDSII — living in one open toolchain. GitHub
A multi-agent RTL framework built on two structured IRs beats prior LLM hardware-generation results
The framework decomposes a design through an Architectural Sketch (module topology and interconnect) and an Operational Specification (per-module function and interfaces), then runs a multi-agent debug loop where agents can choose which simulation signals to probe when a run fails. On Verilog-Eval it reports a 95.5% pass@5, ahead of current LLM hardware-generation frameworks, and the authors add a new case study spanning more complex, realistic designs than the benchmark alone covers. arXiv
An LLM search framework finds a real improvement to a state-of-the-art routing algorithm
FABO asks whether language-model-guided search can improve on SALT, the standard constructive algorithm for timing-driven routing-tree construction, using an agent framework that pairs parallel exploration with independent checking. It surfaces a structural gap: SALT repairs one sink path at a time and never jointly decides where paths sharing root-side wire should split, which can duplicate wire. The resulting joint breakpoint optimization reduces wirelength across 1.29 million ICCAD15 nets, with a fast variant identifying most of the gain at 1.3x SALT's runtime. Code is released. arXiv · GitHub
A reproducible PPA study finds RTL-level clock gating can pass simulation and still be wrong at gate level
On an open-source openMSP430 core synthesized in 32nm, hand-written behavioral clock gating passes all ten self-checking RTL testcases identically to the ungated baseline — then the gated multiplier result reads zero at the gate level, a hold race from the late latch-plus-AND gated clock. The failure holds across eight simulation configurations, including full SDF back-annotation, so it isn't a simulator-setting artifact. Tool-inserted integrated clock-gating cells pass cleanly at both levels and cut dynamic power 74-81% at every process corner tested; the paper's point is that the two gating styles are treated as interchangeable and aren't. arXiv
A 2002 open problem in equivalence checking gets a closed-form, polynomial-time solution
Probabilistic combinational equivalence checking asks how many Boolean functions remain consistent with a set of spectral observations; a 2002 paper posed the general counting problem and solved only two special cases, leaving the rest exponential in the number of observations. This paper reparameterizes onto block sums, turning the dependence between nested spectral coefficients into locality, and counts the surviving functions exactly in time polynomial in the truth-table size — checked against exhaustive enumeration and the original 2002 tables. The same recursion applies to key counting for logic-locked netlists. arXiv
A calibrated energy law argues memory, not arithmetic, is what a computation actually pays for
The paper states one law: the energy of a computation is at least its operations, plus rent on every live bit for as long as it's held, plus fare on every bit moved — then calibrates it against a synthesized 45nm processor's measured storage costs. Under the model, exact attention's quadratic cost in context length is the fare on re-reading every past token, and the paper estimates that fare overtakes a model's own arithmetic near 10^4 tokens: a specific claim about where long-context serving becomes bandwidth-bound, not a general scaling-law aphorism. arXiv
Also noted
- cocotb 2.1.0 shipped, the Python HDL verification framework's latest point release — GitHub
- Beacon, an LLM multi-agent framework for heterogeneous multi-chiplet accelerator design-space exploration, reports cutting a composite latency-energy-cost objective 25-93% versus random search, Bayesian optimization, and reinforcement learning under the same iteration budget — arXiv
- Griotte formalizes CHERIoT's compartmentalization guarantees and proves a specification for its cross-compartment switcher enforces them — arXiv
- KORD, a protocol-hardware co-design, collapses dealerless function-secret-sharing key generation to a single interaction round via special-purpose chips, cutting per-key communication 7,633-70,274x over the prior distributed protocol — arXiv
- Chips and Cheese's Hot Chips 2026 coverage continued: an interview with IBM's Christian Zoellin and Christian Jacobi, and Samsung/XCENA's near-memory-compute CXL device — IBM interview · XCENA/Samsung CXL
- EE Times looks at how AI demand is reshaping the semiconductor patent landscape, from Nvidia's CUDA-moat filings to a surge in Chinese applications — EE Times
- The Chip Letter reports results from a 2023 reader poll asking where RISC-V will be in 20 years — The Chip Letter
- Two small RTL-tuned open models surfaced on Hugging Face this week — Gemma-3-270m-RTL-Tune · rtl-flutter-0.2
- GitHub discovery surfaced a Chisel-based LA32R out-of-order core built for China's NSCSCC 2026 student competition, and a Codex-first, vendor-neutral RTL coding and verification skill — YeXiHuCore · RTL-ASS
- ISSCC 2027's CFP deadline is 13 days out — ISSCC
- IEDM 2026's notification date is 13 days out — IEDM
Landscape watch
- SEC Form D: Datavault AI Inc. (DVLT) filed, matched keyword "semiconductor" — SEC EDGAR
72 items considered: 35 arXiv · 22 RSS · 10 GitHub · 2 Hugging Face · 2 conferences · 1 SEC Form D · 0 Reddit · 0 HN · 0 OpenAlex · 0 PyPI · 0 crates.io · 0 USPTO patents. No adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) ran today and are not due again until 2026-09-09. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.