What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
An agentic LLM took a post-quantum crypto accelerator from RTL to a bring-up FPGA — and exposed a hole in the standard test gate
Known-answer tests (KATs) only exercise the fixed seeds they ship with, but ML-DSA's rejection-sampling signing loop takes a different path depending on the message, so an accelerator can pass every KAT while a timing race hides behind a depth the seeds never reach. The authors found exactly that: a norm check that ran slower than its block-RAM read, surfacing only at the fifth reject-loop iteration under a randomized adversarial soak — 301,343 data-dependent signings, zero escapes, once the gate was replaced with a byte-exact oracle. Separately, they log 232 agentic-LLM-driven design runs on a real Kintex-7 FPGA carrying both ML-KEM-768 and ML-DSA-65, RTL through PCIe bring-up at 98.5% slice occupancy: 71.6% success overall, split along what they call a hardware-coupling gradient — 77-85% on documentation and research tasks against 50-53% on synthesis and bring-up, where corrective feedback is hardest to observe. arXiv
A physical-aware logic synthesis GNN reports double-digit PPA gains inside Berkeley's ABC
Logic synthesis normally optimizes against wire-load models that don't know where gates will actually land. LevelSyn folds physical awareness in earlier: a level-asynchronous graph neural network trained on and-inverter-graph structure predicts gate coordinates directly, feeding a wirelength-driven synthesis pass built into ABC. On the EPFL benchmark suite it reports a 6.89% average power reduction and a 27.48% timing-delay improvement over prior methods, with predicted layout correlating 99.59% against post-place-and-route results. arXiv
A matched-controls study finds a "smart" hardware prefetcher isn't smarter than a gated classical one
Learned cache prefetchers are usually benchmarked against classical predictors that fire on every prediction, which conflates the model's accuracy with whether it's allowed to act at all. This paper applies the same admission gate to both a 257-parameter online MLP and a classical stride predictor and the neural model's edge disappears — indistinguishable from gated stride on random traffic, slower on most regular streams. The gate, not the predictor, is doing the useful work. arXiv
A dictionary-guided repair system fixes an HDL bug a prior tool couldn't, 18x faster on a shared benchmark
Automated HDL repair tools tend to either mutate source blindly (mostly generating code that won't compile) or lean on synthesis and templates that limit what they can fix. This system pairs an ANTLR-derived, DUT-specific mutation vocabulary with fault localization from a single diverging simulation run, exhausting targeted dictionary mutations before falling back to genetic search. On the CirFix benchmark suite it produces correct, oracle-passing repairs on 14 bug variants — including a six-edit multi-bug case CirFix itself cannot repair — and is 18x faster than CirFix on a shared two-edit variant. arXiv
Batching candidate evaluation cuts timing-aware logic-rewrite selection time by up to 30%
SDF-annotated switching simulation can tell functionally equivalent rewrite candidates apart by their timing, but scoring every candidate means repeating timing, compilation, and replay for each one. Batch Before You Time compiles all candidates for one rewrite decision into a single zero-delay proxy image, falling back to the full timed chain only when the proxy result is ambiguous. Across a 12-sequence holdout it cuts complete candidate-selection time 18.05% on average (up to 30.25% at the design level) while matching exhaustive timed selection on all 250 evaluated decisions. arXiv
Also noted
- SiliconCompiler 0.38.7 shrinks its tool container images (stripped symbols, dropped build-only dependencies) and gives Chisel its own JRE instead of borrowing Surelog's, two days after 0.38.6 shipped the LECFlow equivalence-check flow — GitHub
- CIRCT's firtool-1.158.0 adds a FIRRTL gated-clock-conversion utility and a Registry MLIR type; Chisel v7.15.0 is a routine docs-and-dependency release that follows — CIRCT · Chisel
- TechWorks is corralling U.K. chip industry groups under a new umbrella body, UKSIA, as sector funding reported a 65% jump — EE Times
79 items considered: 48 arXiv · 21 RSS · 8 GitHub · 1 HN · 1 crates.io · 0 conferences · 0 Hugging Face · 0 PyPI · 0 OpenAlex · 0 Reddit · 0 USPTO patents · 0 SEC Form D. No adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) are not due again until 2026-09-09. Two arXiv papers already covered in the 2026-09-02 brief (analog-db, the version-space equivalence-checking result) resurfaced in today's fetch window with no material new development and are excluded here. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.