What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Yosys 0.69 ships, cutting a batch of legacy synthesis passes
The open RTL synthesis suite's 0.69 release removes several long-carried passes and options — coolrunner2 and greenpak4 synthesis, nlutmap, the sum-of-products parameters in abc, and the -retime/-noabc9/ -abc2/-abc flags — while adding -sv2023 support to the Verific front end. A cleanup release rather than a feature release: the project is shedding vendor-specific and superseded paths as it keeps its SystemVerilog front end current. GitHub
A history-aware offline-RL router policy cuts detailed-routing violations 92% on dense layouts
Detailed routing is a persistent bottleneck in physical design, and existing RL-based cost-tuning approaches degrade on the densest, hardest-to-route layouts. This work adds a lightweight LSTM on top of a conservative Q-learning policy so it retains sequence context across routing iterations, and reports it drops in with minimal changes to any cost-based router. On held-out dense-placement and low-guide-quality test cases it cuts design rule violations by an average of 92% over the top public baseline while also cutting runtime 10%. arXiv
A 28nm digital Ising accelerator scales to 27,648 spins across four chips
Multichip Ising accelerators trade off connectivity, precision, and scale; this one raises the coefficient precision to 10 bits and native connectivity to degree-15 (Pegasus graph) over prior degree-8, 5-bit designs, using a time-multiplexed spin-update array with local SRAM and scheduled interchip transfers. It reports 41.5G updates/s at 1.2pJ/update, and a four-chip planted-MaxCut trace finding the known solution for 27,069 nodes in 3.3μs. arXiv
NVIDIA opens a native Rust track for CUDA GPU kernels
NVIDIA is adding Rust as a first-class option for writing GPU kernels alongside its existing CUDA C++ and CUDA Python toolchains. The framing is explicit: C++ and Python are already mature, enterprise-grade paths, and Rust becomes a third supported track rather than a community side-project — worth watching for anyone building GPU-kernel-generation tooling that currently targets only C++ or Python. NVIDIA
Token cost is becoming its own line item in EDA budgets
Semiconductor Engineering flags a specific, quiet shift: per-token inference cost is now large enough to move EDA design budgets on its own, separate from license and compute-cluster spend, and the piece says what comes next isn't yet clear. Short on detail, but the framing matters for anyone selling or building agentic EDA tooling — it names token cost as a budget category chip teams now have to plan around. Semiconductor Engineering
Also noted
- Arm issues a correction on its C2-Ultra reveal: the maximum IPC gain over C1-Ultra is 7%, with memory-bandwidth improvement not folded into that figure — Chips and Cheese
- Semiconductor Engineering asks whether GPUs keep dominating AI compute as Google, Amazon, and now OpenAI's own silicon gain share — Semiconductor Engineering
- Chipstrat argues most semiconductor markets settle into a three-player oligopoly equilibrium — Chipstrat
- EE Times: a strategy paper urges Canada to align procurement, talent, and funding behind its own semiconductor strengths as part of its sovereign-AI ambitions — EE Times
- A taxonomy paper examines hardware-Trojan threats to multi-chiplet photonic neural-network accelerators across confidentiality, integrity, and availability, without reporting a measured attack or defense yet — arXiv
- OTTER pairs a low- and high-drive-current transistor in a 2T1R cell for reliable TaOx-RRAM in-memory computing at 28nm — arXiv
- A differentiable partitioning framework jointly optimizes tier assignment and hybrid-bonding terminal placement for 3D-IC layouts — arXiv
- GMSBench proposes a standardized benchmark for evaluating GPU memory safety techniques — arXiv
- BLINK uses batch-normalization-based integrity checkpoints to detect and mitigate weight corruption — aging, soft errors, bit-flip attacks — in DNN accelerators — arXiv
- EStream virtualizes experts to fit MoE prefill onto mobile NPUs whose compute graphs are fixed at compile time — arXiv
- Another High-Bandwidth Flash paper, this one for generative-recommendation KV-cache serving — the HBF drumbeat continues — arXiv
- Semiconductor Engineering on the friction between hardware-level security controls and digital-forensics investigations — Semiconductor Engineering
- A trio of small RTL/VLSI-tuned open models surfaced on Hugging Face this window, all early and low-engagement — llama2-7b-sft-verilog · qwen_vlsi_curriculum_v4 · qwen_vlsi_curriculum_v4_1
- Hacker News: a deep-dive walkthrough of reverse-engineering an ASIC — HN
56 items considered: 30 arXiv · 14 RSS · 4 HN · 3 GitHub · 3 Hugging Face · 1 PyPI · 1 crates.io · 0 conferences · 0 OpenAlex · 0 Reddit · 0 USPTO patents · 0 SEC Form D. No adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) ran today and matched nothing, so Landscape watch is omitted. FINN's v1.0.0-alpha release, already covered as this week's headline in the 2026-09-07 brief, resurfaced in today's GitHub fetch with no material new development and is excluded here. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.