What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
AutoTrans automates AI-assisted translation of RISC-V security assertions, then gates every output through formal verification
Manual translation of a verified security assertion from one RISC-V core to another takes hours, and raw LLM translation is fast but unreliable — it invents port names absent from the target RTL and produces different output run to run. AutoTrans fixes the first failure with a lightweight regex-based signal extractor that pins down real RTL signals before prompting, and the second with a byte-identical prompt template plus pinned inference parameters. Every generated assertion still has to clear JasperGold formal property verification before it counts, so a hallucinated signal fails the gate instead of silently entering the result set. The authors ran it on Deepseek V4 translating assertions between IBEX and NS31A RISC-V cores. arXiv
Two papers push agentic HLS design past code generation, and initial results say the easy benchmarks are already solved
HLS-Eval already existed as a benchmark for LLMs on high-level-synthesis tasks; this extension wraps it in an agentic harness (mini-swe-agent) so a model can invoke a C++ compiler, self-verify, and iterate instead of generating once and stopping. The headline finding: open-source LLMs paired with the agentic harness solve every simple HLS generation task in the existing benchmark, which the authors read as a sign the benchmark needs to get harder before it can distinguish models. A companion paper, HLSFactory-Agent, tackles the upstream bottleneck — the training and eval data agentic HLS work depends on — by using an LLM agent to extract standalone HLS designs from arbitrary GitHub repos and academic codebases instead of doing that extraction by hand. arXiv HLS-Eval · arXiv HLSFactory-Agent
Fengshui codesigns a chiplet pool and the bespoke accelerators built from it, cutting energy-delay-cost 97.8% over homogeneous baselines
Operator-level disaggregation — tailoring microarchitecture and memory hierarchy to each ML operator — beats homogeneous hardware on latency and energy, but building a bespoke accelerator for every operator is normally too expensive to justify. Fengshui breaks the resulting chicken-and-egg problem (a chiplet pool's value depends on the accelerators built from it, and accelerator quality depends on the available chiplets) by jointly optimizing both, validating designs with actual place-and-route rather than stopping at architectural estimates. With just 8 chiplets — network switches, PIM units, and accelerators of varying microarchitecture — the generated designs report reductions of 48.5% energy, 88.1% energy-cost product, 93.0% energy-delay product, and 97.8% energy-delay-cost product against homogeneous accelerator baselines. arXiv
AccelForge unifies accelerator device/circuit/architecture modeling and mapping search into one fast, extensible framework
Iterating on an AI accelerator design means evaluating device, circuit, and architecture choices together with how a workload maps onto the hardware, and existing modeling frameworks tend to cover only part of that stack. AccelForge folds multiple prior frameworks into one: composable, user-modifiable models across the device/circuit/architecture levels, and mappers the authors say run orders of magnitude faster than prior tools while staying accurate. It's a Python codebase aimed at researchers who want to extend the model or the mapper rather than treat either as a black box. arXiv
Huawei's first LogicFolding phone chip tests whether stacking circuits can substitute for the node shrinks US sanctions block
The Kirin 9050 Pro, debuting in Huawei's Mate XT 2 trifold phone, is the first commercial chip built on Huawei's "LogicFolding" architecture — reported as layering circuits on top of each other to add performance without a smaller process node. That's the framing analysts are watching most closely: Huawei's HiSilicon unit has been cut off from leading-edge foundry access, so an architecture-level workaround to squeeze more performance from the process nodes it can still reach is a specific, testable claim about how far design can substitute for fabrication under sanctions. SCMP LogicFolding test · SCMP chip philosophy · SCMP computing reset
Also noted
- PATTON, a PIM runtime, integrates production LLM-serving KV-cache lifecycle management with commodity processing-in-memory, reporting a 1.95x speedup and 4.83x higher energy efficiency over evaluated baselines — arXiv
- UNISON, a near-memory scheduler for LLM-agent session KV residency, reports hit-rate gains up to 23.1 points and TTFT cuts up to 89% on long-horizon agent traces — arXiv
- Entwine coordinates GPU tile computation and fine-grained communication, reporting a 1.232x geomean speedup over cuBLAS+NCCL on tensor-parallel LLM workloads; open-source planned — arXiv
- REACH, a controller microarchitecture for long-span ECC on HBM, reports 55.8% less controller area than a direct long-code baseline at the same error-correction target — arXiv
- CertiFlash, mechanized in the Rocq proof assistant, gives flash- translation-layer designers one machine-checked proof covering isolation, integrity, and ownership instead of re-verifying each modification from scratch — arXiv
- DiffLUT-Net trains FPGA LUT networks — both truth tables and input connectivity — end to end and exports directly to synthesizable Verilog; code released — arXiv
- Ozaki 2.5 engineers the residue-conversion path for emulating FP64 matrix multiplication on FP8 tensor cores, modeling (not yet measuring) a hardware fast path for NVIDIA's upcoming Rubin GPU — arXiv
- A joint academia-industry position paper argues core silicon-design fundamentals matter more, not less, as agentic AI reshapes chip-design training and practice — arXiv
- HeteroReason disaggregates speculative-decoding reasoning across an FPGA draft engine and GPU process-reward/target models — OpenAlex/Zenodo
- CIRCT's firtool-1.159.0 lands a FIRRTL gated-clock-conversion pass and a Registry MLIR type — GitHub
- amaranth-lang/amaranth ships 0.5.10, a routine point release — GitHub
- EE Times recaps DAC 2026's agentic-EDA sessions, arguing the industry has reason for optimism on agents, engines, and trust — EE Times
- ADI acquires Alif Semiconductor for $1.35B, pairing analog sensing with low-power edge-AI processors — EE Times
- Hacker News: a from-scratch RISC-V emulator and Linux boot walkthrough draws unusually engaged discussion — HN
- Semiconductor Engineering's weekly roundup flags a busy week: 12-inch high-NA EUV masks, a $60B Qualcomm-AWS custom-silicon deal, Ayar Labs' scale-up deal, and Amkor's expansion, among others — Semiconductor Engineering
104 items considered: 50 arXiv · 30 RSS · 16 OpenAlex · 5 GitHub · 2 HN · 1 crates.io · 0 conferences · 0 Hugging Face · 0 PyPI · 0 Reddit · 0 USPTO patents · 0 SEC Form D. No adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-09 and are not due again until 2026-09-16, so Landscape watch is omitted. Several items already covered in the 2026-09-09 brief resurfaced in today's fetch window with no material new development and are excluded here: Yosys 0.69 and the CUDA Rust track (both headlines), the history-aware offline- RL router and the 28nm digital Ising accelerator (both headlines), Arm's C2-Ultra correction, Chipstrat's oligopoly-equilibrium piece, and GMSBench (all also-noted). Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.