What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Architect Labs says its AI can drag a custom chip design from years to two weeks
The company's pitch for its Redwood system is a specific, checkable timeline claim: what a custom-chip design cycle normally takes in years, the AI-assisted flow does in two weeks. EE Times reports the claim without independent verification, so treat "years to weeks" as a vendor number until an outside team or customer confirms it against a real tapeout, not a demo. EE Times
SiliconCompiler 0.38.8 splits its cache directory and adds run cancellation
The open, Python-driven ASIC/FPGA build system's latest release separates the downloaded-data cache from the per-tool cache (each now addressable by a hash of the task's own configuration), adds a cluster-wide cache path and a docker compose deployment for its server/scheduler stack, and gives the scheduler the ability to cancel a running node along with its descendants instead of only refusing to start new ones. Incremental infrastructure work rather than a new flow — the project has shipped equivalence-checking and ML-front-end features in prior releases (2026-09-02, 2026-09-04); this one is about running the tool at scale without leaking disk or cluster time. GitHub
Beijing's top EDA vendor says it's using agentic AI to accelerate chip design
Empyrean Technology's chairman tells SCMP the company is applying AI-optimized algorithms and agentic tools inside its EDA software as part of a broader Chinese push to reduce dependence on foreign design tools. Short on technical detail — no benchmark, no named flow stage — but notable as a public claim from the country's largest domestic EDA vendor that agentic AI is already in its product, not just its roadmap. SCMP
A pre-silicon taint-tracking method from Princeton, MIT, and EPFL targets RTL security testing
Register-transfer-level simulation is the standard place to test a design before fabrication, but checking for confidentiality and integrity properties usually means hand-instrumenting taint logic into the RTL. This work automates that instrumentation so information-flow properties can be tested efficiently during ordinary pre-silicon simulation, aimed at catching hardware security bugs before tapeout rather than after. arXiv via Semiconductor Engineering
CHIPSMORE pairs compute-in-interconnect and compute-in-memory chiplets for multi-request LLM serving
Researchers at the National University of Singapore built an inference accelerator that mixes compute-in-interconnect and compute-in-memory chiplets to serve both base-mode and LoRA-adapted requests under one architecture, rather than provisioning separate hardware paths for each inference mode. The paper targets the specific gap between how LLM serving actually mixes requests and how most inference-accelerator designs still assume a single, uniform workload. Semiconductor Engineering
Chinese researchers report a 100x endurance jump in a ferroelectric memory candidate
A wurtzite-ferroelectric device demonstrated more than 10 billion write cycles, which the team frames as removing a reliability barrier that has kept this class of emerging memory out of high-performance computing roles. It's a materials/device result, not a shipped part — the interesting question is whether the endurance number survives integration into an actual memory array at scale. SCMP
Also noted
- Jane Street is running a public "design a chip" competition around a protocol-emulator ASIC — HN · Jane Street
- penberg/titania, a new GitHub project, aims to build a complete LLM system "from transformer to transistor" simple enough for one person to understand — early, 87 stars — GitHub
- Besxar, founded by an ex-OpenAI technical director, completed its first SpaceX flight testing compound-semiconductor wafer growth in space vacuum and recovered samples without contamination — EE Times · EE Times video
- RapidGEMM, a grouped-GEMM kernel for MoE training, reports up to 1.27x speedup over prior kernels on B200 GPUs; code released — OpenAlex
- A review from Chinese and international authors surveys silicon-photonic optical I/O for short-reach AI-cluster interconnects — OpenAlex
- NYCU and TSMC researchers report molybdenum-based quasi phase-only EUV masks with higher reflectivity and lower absorption than current phase-shift masks — Semiconductor Engineering
- Semiconductor Engineering looks at chiplet-level health and performance monitoring as advanced packaging makes a system-in-package harder to observe as one part — Semiconductor Engineering
- NVIDIA writes up dropless MoE training in JAX using its Transformer Engine — NVIDIA
- Chipstrat argues consumer-facing agent products (Grok Bot, Meta Muse) will reshape demand for CPUs, accelerators, memory, and packaging — Chipstrat
- Ken Shirriff reverse-engineers the scale instruction in Intel's 8087 floating-point chip's microcode — Ken Shirriff
- Two more low-engagement RTL/EDA artifacts surfaced on Hugging Face: a Qwen2.5-7B RTL/VLSI LoRA and an EDA-trajectory dataset — qwen2.5-7b-rtl-vlsi-lora · classic-eda-c-trajectories
40 items considered: 25 RSS · 7 OpenAlex · 4 GitHub · 2 HN · 2 Hugging Face · 0 conferences · 0 PyPI · 0 crates.io · 0 Reddit · 0 USPTO patents · 0 SEC Form D. arXiv failed this run (HTTP 429 on cs.AR and the cs.LG/cs.PL/cs.DC query, timeout on cs.ET) — 0 items from a source that normally supplies the largest share of the brief, so today's selection leans on RSS/OpenAlex/SCMP coverage of the same underlying papers where available. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-09 and are not due again until 2026-09-16, so Landscape watch is omitted. Four items already covered in the 2026-09-11 brief resurfaced in today's fetch window with no material new development and are excluded here: the Huawei Kirin/ LogicFolding "computing reset" piece, the HeteroReason FPGA-GPU speculative-reasoning artifact, the REACH HBM-ECC controller paper, and EE Times' DAC 2026 agentic-EDA recap (all exact URL repeats). The iree 3.12.0 release-candidate train, first noted 2026-09-07, continues (rc20260914, three RCs since 2026-09-11) with no stable release yet and is excluded pending one. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.