What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
OpenAI says LLMs cut its Jalapeño chip's RTL-to-silicon timeline to nine months
IEEE Spectrum's deep dive on OpenAI's Jalapeño accelerator — first unveiled 2026-08-25, delivering up to 13.4 petaflops of 4-bit compute over 232GB of memory at 15.4TB/s — puts a number on the design side rather than the performance side: first architecture concept to first silicon took under 20 months, and only nine of those months separated first RTL from working chip, which OpenAI attributes to LLM-accelerated design. OpenAI's own latency claims against Nvidia's GB300 (up to 3.6x lower end-to-end latency) are vendor benchmarks pending fleet-scale confirmation; the design-timeline claim is the more checkable one and the one most relevant to anyone building agentic chip-design tooling. IEEE Spectrum
SK Hynix is in talks with Intel to make memory chips in the US for the first time
Reuters reports the two companies are discussing a deal that would have SK Hynix manufacture memory domestically in the US, something it has never done before. No terms or timeline yet, but it's a specific, checkable claim about US memory fab capacity that would matter to anyone tracking where HBM and DRAM supply actually gets built as AI accelerator demand strains both. Reddit r/hardware · Reuters
Altera confidentially files for a US IPO
Reuters reports the FPGA maker — spun out of Intel and since taken over by Silver Lake — has confidentially filed for a US IPO, with investors positioned to use the offering as a read on AI-driven FPGA demand. A confidential filing means terms and timing are still unknown, but it's the clearest signal yet that Altera's owners see a public listing as near-term rather than aspirational. Reddit r/FPGA · Reuters
A Gherkin-based spec workflow more than doubles LLM-generated RTL's pass rate against formal checks
Natural-language hardware specs are ambiguous in ways that hurt LLM output quality, and fully formal specs fix the ambiguity but are hard to write and read. This work introduces "Formal Verification Gherkin Scenarios" — a controlled natural language sitting between the two — as the input to an LLM-enabled behavior-driven hardware workflow, then feeds the result through formal property verification. Against other established LLM-based methods, the authors report 2.48x better functional correctness in the generated RTL and 2.54x better formal coverage in the generated assertions. arXiv
SpecLens tightens LLM Verilog generation by mining disagreement between candidate implementations
Most LLM Verilog-generation work strengthens the prompt with retrieval, self-planning, or few-shot examples — external scaffolding around a generic spec. SpecLens instead generates multiple candidate implementations from the same natural-language spec, analyzes where they behaviorally diverge, and turns those divergence points into task-specific constraints fed back into generation, using only the original spec as its external source of truth. On VerilogEval v2.0 it reports an 86.2% functional pass@1 with o3-mini-medium and 89.4% with o3-mini-high — a 3.6-3.8 point gain over prior SOTA methods — without relying on iterative compile-repair loops. arXiv
An ML-assisted DTCO framework adds CFET and multi-row-height standard cells to the optimization loop
Design-technology co-optimization means jointly tuning process technology and design choices for power, performance, and area, and block-level PPA evaluation is the expensive step in that loop. This framework uses machine learning to identify optimal DTCO parameter sets in real time and adds a faster standard-cell-library generator that supports both complementary-FET-based cells and multi-row-height cells — two cell styles relevant to the process nodes chipmakers are actually moving toward, not just conventional planar layouts. OpenAlex
South Korea targets a $598 billion semiconductor cluster by 2030
A regional development plan for southwest Korea puts a number on the country's next chip-manufacturing buildout: $598 billion aimed at 2030 production. As with any long-horizon industrial plan, the figure is a target rather than committed capital, but it's a concrete marker for how much capacity Korea is betting AI demand will require by the end of the decade. Reddit r/hardware · Herald
DeepSeek-V4-Flash gets a correctness fix and a performance pass on AMD's older CDNA2 GPUs
Getting an open MoE model running well on non-NVIDIA hardware is its own engineering project: the authors found their fast execution path for DeepSeek-V4-Flash on AMD MI250 (gfx90a/CDNA2) GPUs was numerically wrong because of a routed-expert weight-layout mismatch, fixed it, then tuned decode and prefill separately (packed FP4 weights, INT8 activation quantization, CDNA2-specific dot-product instructions, retuned expert sorting). Reported results on four MI250 GCDs: ~74.5 tok/s native autoregressive decode and ~2,234 input tok/s prefill on a 4,604-token prompt — with the paper's honest framing that older-generation hardware is bottlenecked as much by FP4 format mismatches and synchronization overhead as by raw memory bandwidth. arXiv
Also noted
- SCHERI extends CHERI's capability-based security model with a provably secure defense against speculative-execution attacks under a constant-time policy — arXiv
- Accurate Models of AMD Matrix Cores characterizes the undocumented numerical behavior (rounding, accumulator width, subnormal handling) of AMD's CDNA1/2/3 matrix multipliers and ships validated software models reproducing hardware results bit-for-bit — arXiv
- Another High-Bandwidth Flash paper, this one sizing a trillion-parameter MoE inference box around HBF instead of HBM — the drumbeat continues — arXiv
- Budgeted Express-Mesh proposes traffic-aware link placement and deadlock-free adaptive routing for mesh interconnects under a fixed link budget — arXiv
- A fault-injection study on multi-tenant FPGAs demonstrates persistent attacks across tenants and proposes an ASCON-based defense — OpenAlex
- A GPU-accelerated gate-level power analysis method uses event-density- aware partitioning and kernel fusion to speed up time-based power estimation — OpenAlex
- Three new Rust crates (forge-sexpr, forge-model, hauksbee-forge-codegen) form a byte-stable KiCad file-format toolkit — lossless s-expression parsing, a typed schematic/board model, and schematic/board codegen — forge-sexpr · forge-model · hauksbee-forge-codegen
- Hacker News: a security researcher cracks the PlayStation 2's Mechacon security chip wide open after 26 years — HN
- Hacker News: a from-scratch FPGA recreation of 1990s Voodoo Graphics and a period-accurate gaming PC — HN
110 items considered: 37 arXiv · 24 Reddit · 22 RSS · 17 OpenAlex · 4 crates.io · 3 GitHub · 2 HN · 1 Hugging Face · 0 conferences · 0 PyPI · 0 USPTO patents · 0 SEC Form D. The weekly landscape sources (USPTO patents, SEC Form D) ran today: patents matched nothing across its four tracked assignees (NVIDIA, Groq, Cerebras, Tenstorrent), and Form D matched nothing on five of its eight search terms — the other three (ASIC, tapeout, neural processing) failed with HTTP 500 rather than returning zero — so Landscape watch is omitted rather than reported empty. Three items already covered in the 2026-09-14 brief resurfaced in today's fetch window with no material new development and are excluded here: SiliconCompiler's v0.38.8 release (exact repeat), and SCMP's Chinese-ferroelectric-memory-endurance and Empyrean/Beijing agentic-chip-design stories (both exact URL repeats). The iree 3.12.0 release-candidate train, first noted 2026-09-07, continues (rc20260916, three more RCs since 2026-09-14) with no stable release yet and remains excluded pending one. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.