What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Huawei unveils a 1-million-processor "single computer" architecture and pulls its next Ascend chip forward nine months
Huawei introduced the Peerium Computing Architecture, which pairs nested parallelism, unified memory addressing, and peer-to-peer links so that up to a million processors present as one machine, with its UnifiedBus interconnect as the fabric between processors, memory, and storage. SCMP frames it as a route around US chip curbs: scale out on interconnect rather than on leading-edge nodes. Huawei also said the Ascend 960DT training chip, with "performance doubling", will be ready in Q1 2027, three quarters earlier than planned. An accompanying arXiv paper (Nested Parallel von Neumann Architecture and Nested BSP) is the architectural argument; the launch numbers are Huawei's own and nothing here is independently benchmarked. SCMP: Peerium and UnifiedBus · SCMP: Ascend 960DT · Tech Xplore · arXiv
A paper tests whether an AI architect is reasoning about the machine or just searching knobs
AutoTuring gives one agent the same 15-dimensional accelerator design space twice: once with named architectural knobs and simulator counters, once as anonymous variables on [0,1], with the evaluator and optima held identical. On a nine-kernel FP16 GEMM basket the informed agent beats a modeled H200 by 5.4% and its blind counterpart by 12.3% while using 70.1% fewer simulator calls. A critic loop recovers most of the blind agent's gap, so architectural knowledge and structured critique look like substitutes, not complements. The authors call it preliminary: five to six runs per condition on a single modeled accelerator. The experimental design is the useful part. arXiv
SiFive and AMD show ROCm AI workloads running on a RISC-V datacenter platform
EE Asia reports a joint SiFive–AMD demonstration of ROCm AI workloads on a RISC-V-based datacenter platform, and it drew the most engagement of any open-silicon item in the window on r/RISCV. The item as fetched carries no performance numbers, so it reads as a software-stack compatibility milestone rather than a benchmark: AMD's GPU software stack now has a RISC-V host in public view. Worth watching for what ships, not what's shown. EE Asia · r/RISCV · r/hardware
A CP-SAT solver synthesizes GPU instruction encodings that cut Blackwell kernel footprint by 33%
The paper treats instruction layout as a constrained slot-assignment problem and applies it to NVIDIA SASS, normalizing public encoding text into a machine-readable spec and validating a disassembler against nvdisasm on 3.78M instructions, released as an open benchmark. On 142 Blackwell kernels, variable-length encoding shrinks instruction footprint 33%; fixed-length encoding cuts decoder area 16% against the observed 128-bit layout. The generated fetch/decode RTL meets 1.5 GHz in TSMC 22 nm. These are the authors' synthesis results, not silicon. arXiv
Two verification papers: an RL-tuned testbench generator, and a benchmark of 2,608 injected RTL bugs
CovR trains a model on 16,514 spec–RTL–reasoning–testbench tuples with simulator coverage as the reward, reporting 93.81% cov@10 on VerilogEval and RTLLM V2.0 and 87.76% on CVDP, ahead of prior approaches by 7.97 and 3.59 points. VeriBugBench builds RTL debugging benchmarks from 45 open-source projects using 19 mutation operators derived from real bug-fix histories, yielding 2,608 executable single-fault instances with source-level ground truth. One generates stimulus to hit coverage, the other supplies faulty designs to debug against; both are arXiv preprints. CovR · VeriBugBench
Magic 8.3.684 fixes LEF writes that silently dropped via layers
The release corrects a line in lefWrite that made Magic ignore contact types, so via layers (as ports or obstructions) could not be written to LEF files regardless of tech-file or tech-LEF setup. The maintainer says he can't recall why the option was there originally, and that enabling or disabling vias in the output belongs in the technology LEF, not in Magic's code. Anyone round-tripping layouts through Magic and LEF on an open PDK flow should check earlier outputs. Magic 8.3.684
Also noted
- Rosetta, a multi-agent LLM pipeline, turns an architecture paper's PDF into a first-principles analytical performance model with no human intervention — arXiv
- "AI for Science with GPT-6 Astra" has an agent workflow propose thermal structures for a 2D CFET inverter, cutting peak temperature rise by 1.67 K at fixed metal volume — arXiv
- Locus generates ASIC and FPGA point-addition hardware for arbitrary elliptic curves and explores 1,000 design points for zero-knowledge proofs — arXiv
- MeshKV proposes a network-on-chip KV-cache fabric for transformer decoding accelerators — arXiv
- Two papers evaluate Positive Feedback Adiabatic Logic in 16 nm FinFET with realistic power-clock waveforms — arXiv · arXiv
- A survey covers where RISC-V and machine learning intersect — arXiv
- WACA-UNet adds channel attention to static IR-drop prediction so sparse wire and via resistance cues aren't drowned out — DOI
- Enflame listed on the STAR Market with Tencent holding about 20% and supplying 84% of revenue — r/Semiconductors
- Washington awards $1B to IBM's Anderon for quantum wafer manufacturing — EE Times
- NVIDIA explains how Groq 3 LPX deterministic execution serves high-interactivity inference — NVIDIA
- Hacker News: Bend, a language that uses proofs to block AI mistakes on CPU and GPU, drew 560 points — HN
- r/FPGA and r/RISCV both ran "Doom on an FPGA" posts — r/FPGA
131 items considered: 48 arXiv · 34 RSS · 33 Reddit · 11 OpenAlex · 3 GitHub · 2 HN · 0 conferences · 0 Hugging Face · 0 PyPI · 0 crates.io · 0 lab news pages · 0 USPTO patents · 0 SEC Form D. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-16 and were not due, so Landscape watch is omitted. Excluded as already covered: the from-scratch Voodoo Graphics FPGA recreation on Hacker News (2026-09-16 also-noted), the SpecLens, SCHERI, and Budgeted Express-Mesh papers (2026-09-16), and the iree 3.12.0 and tt-metal v0.79.0 release-candidate trains, which have no stable release yet. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.