What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
China's CXMT says its new DRAM platform is in mass production, closing on Samsung and SK Hynix
Changxin Memory Technologies said it moved its fifth-generation (G5) manufacturing platform into mass production, claiming at least 50% more dies per wafer than the prior generation while holding better power and performance. CXMT frames this as narrowing the node gap with Samsung and SK Hynix. These are the company's own figures, not independently verified — but a wafer-level density jump of that size, if it holds up, matters for anyone tracking whether China's memory industry still needs Western toolchains to keep pace. SCMP · r/hardware
Chinese researchers report early progress on sub-3nm chips without EUV lithography
SCMP reports Chinese researchers pushing process nodes below 3nm using older, non-EUV lithography tools — working around the ASML export ban rather than through it. This is early-stage R&D, not a shipped commercial node, and the specifics of what "sub-3nm" means here (which metric, which device) aren't independently confirmed. Worth tracking as a leading indicator of how much runway alternate-path lithography actually has, not as a finished product. SCMP
Intel puts High-NA EUV into production on Panther Lake; stitching across larger masks is still unproven
Panther Lake is the first high-volume chip validated in production on ASML's High-NA EUV scanners, after years of pilot-line-only use. EE Times flags the next hurdle: electrical stitching across larger masks, needed to print bigger die on High-NA tools, hasn't been demonstrated at scale yet. Getting High-NA into a shipping SKU is real progress; whether it scales past today's die sizes is still open. EE Times
An open-source compiler flow doubles FlashAttention throughput on AMD's XDNA NPUs by choosing where tensors live
Researchers mapped FlashAttention onto AMD's XDNA 1 and XDNA 2 spatial NPUs using the open-source IRON and MLIR-AIR compiler flows, comparing four ways to place intermediate tensors across the chip's local memories. Fusing all three attention stages into one kernel that never spills scores back to shared memory reaches 3.62 TFLOP/s on XDNA 2 — twice the baseline IRON design, and 5.3–7.2x the on-chip integrated GPU's energy efficiency at 2K+ tokens. The paper's real contribution is a roofline recipe: compare a mapping's operational intensity against each memory level's ridge point to know when fusion helps and when it's wasted, tested across twelve LLM configurations up to 128K tokens. arXiv
A paper finds LLM agents write better chips when they design in HLS first, then refine down to RTL
The paper compares direct RTL generation against agent-driven HLS design, post-compiler HLS refinement, and post-HLS RTL refinement, then combines the last two into a single pipeline (AHRR). Across an 11-task FPGA benchmark suite, AHRR gets a 2.6x geometric-mean speedup over direct RTL generation. The authors' read: HLS gives the agent design knowledge to work from, and RTL refinement recovers the low-level tuning that abstraction costs. Code and benchmarks are public. arXiv · GitHub
DRC-Aid turns local design-rule-check repair into an agentic, verification-in-the-loop search
Purdue's DRC-Aid frames local DRC repair as a search problem: a deterministic rule engine converts physical-verification tool output into constraints, and an LLM agent proposes geometric fixes that get checked against those constraints before being accepted. It targets the narrow, repetitive class of DRC violations that eat reviewer time in physical design, not layout generation broadly — putting it in the same lineage as the RTL-repair-agent papers that have shown up in recent weeks. Semiconductor Engineering
SiliconCompiler 0.38.9 fixes a rerun failure mode and adds token auth for private dataroots
The release changes how a rerun treats a build directory excluded by from/to/prune options: instead of failing when something depends on an excluded upstream, it now rebuilds that upstream. It also adds token authentication for GitLab and Bitbucket dataroots (fixing tokens sent under the wrong username and logged in cleartext clone URLs), moves pandas into an optional dashboard extra so a default install stays lean, and adds rectilinear-floorplan support to the OpenROAD backend. Housekeeping, but the kind that matters if you're running this in CI. GitHub
imec demos a 100 GHz avalanche photodiode that hits 400 Gbps at 5V
imec built a germanium-on-silicon avalanche photodiode on its 300mm silicon-photonics platform that reaches 100 GHz bandwidth at just 5V, with roughly 2x internal gain and 1.8 A/W responsivity across both O- and C-bands. It demonstrated a net 400 Gbps optical link with a 3 dB sensitivity improvement over a conventional photodiode, using a "deeply-recessed" germanium-in-silicon structure with a sub-100nm multiplication layer that drops the usual charge layer — the design choice that's historically forced a tradeoff between gain, bandwidth, and voltage. It's a device demo on imec's own platform, not a shipping part, but avalanche photodiodes are the hardest piece of an optical receiver to scale, so a bandwidth jump there is a real lever on datacenter interconnect speed. imec
Also noted
- Samsung is expected to more than double HBM4/HBM4E output this year, raising glass-carrier demand 2.5x — r/hardware
- Hygon plots expansion from datacenter chips into robotics — SCMP
- A chiplet co-design framework cuts energy and design cost for AI accelerators (Michigan) — Semiconductor Engineering
- An open benchmark evaluates AI thermal models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech) — Semiconductor Engineering
- A survey covers AI in chip design from code generation to EDA orchestration (Edinburgh) — Semiconductor Engineering
- A unified chiplet network aims to scale neuromorphic computing systems (Heidelberg) — Semiconductor Engineering
- Predicting thermal conductivity in advanced BEOL interconnect stacks (Peking) — Semiconductor Engineering
- Chips and Cheese digs into Qualcomm's Adreno X2 GPU architecture — Chips and Cheese
- Hacker News: every Nvidia GPU has 10 to 30 RISC-V cores inside it — HN
- A multi-scale temporal-convolution-plus-attention model targets instruction-activated hardware Trojan detection — DOI
- Folding approximate logic synthesis into approximate HLS cuts hardware cost 11% on average at the same error bound — arXiv
- COMET offloads packet-arrival tracking for erasure-coded RDMA over lossy WANs entirely onto an FPGA NIC, sustaining 400 Gbps and beyond — arXiv
- CARDAN speeds MoE decoding 1.15–1.7x on AWS Trainium3 by splitting expert weights into vector-quantized and shared-basis low-rank components — arXiv
- Two small open-source EDA tool updates: LazyVerilog LSP adds UVM support, and a follow-up to an open-source gm/Id-based analog multicorner sizing tool — r/FPGA · r/chipdesign
- JH7110/VisionFive 2 gets PowerVR BXE-4-32 GPU and DC8200 display bring-up via out-of-tree kernel patches — r/RISCV
77 items considered: 22 RSS · 28 Reddit · 9 arXiv · 6 lab news pages · 5 GitHub · 3 OpenAlex · 2 HN · 2 Hugging Face · 0 conferences · 0 PyPI · 0 crates.io · 0 USPTO patents · 0 SEC Form D. The OpenAlex groups query hit a rate limit (HTTP 429) this run; the 3 OpenAlex items above are from the primary query only, not a "nothing new" result. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-16 and aren't due again until 2026-09-23, so Landscape watch is omitted. Excluded as already covered: Magic 8.3.684 (same release headlined 2026-09-18), a Semiconductor Engineering write-up of the same history-aware offline-RL routing paper covered 2026-09-09, a Tech Xplore Huawei piece already linked 2026-09-18, and the iree 3.12.0, tt-metal v0.79.0, and TVM v0.27.0 release-candidate trains, none of which have cut a stable release yet. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.