What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
imec's IC-Link joins TSMC's cloud alliance as the first managed-cloud service for mixed-vendor EDA flows
imec's ASIC/silicon-photonics design-and-manufacturing arm, IC-Link, has joined TSMC's Open Innovation Platform (OIP) Cloud Alliance, building on its existing membership in TSMC's 3DFabric, Value Chain (since 2009), and Design Center (since 2007) alliances. It's described as the first managed-cloud service in that alliance supporting a mixed-partner EDA flow — customers get secure cloud access to TSMC's advanced PDKs and scalable compute while keeping their own choice of EDA tools and licenses, with imec managing the infrastructure. No process node or pricing specifics were disclosed. imec
A multi-agent LLM framework sizes analog circuits where classical optimizers fail outright
AgenticSizing decomposes a netlist into functional blocks, extracts reusable design knowledge from the topology, then coordinates role-specialized sizing agents under a planner — mimicking how an analog design team splits the work, rather than treating sizing as one flat optimization. Validated on eight circuits up to 55 transistors and 60 sizing variables, the largest tested. On the LDO benchmark it hit a 60% success rate over an average 83 iterations; the paper reports classical optimizers found no feasible solution at all on that circuit. arXiv
Wafer-scale monolayer MoS2 transistors hit sub-5nm channel length with a subthreshold swing silicon can't match at that scale
Researchers at Carnegie Mellon, University of Florida, MIT, Texas A&M and others report monolayer MoS2 transistors with physical channel lengths below 5nm and a subthreshold swing of 88 mV/dec. Real silicon devices degrade sharply on subthreshold swing as channel length shrinks into this range from short-channel effects; the paper's framing is that this 2D material holds swing performance silicon can't sustain at the same geometry — a wafer-scale demonstration, not a production process. Semiconductor Engineering
Alibaba debuts a new domestic AI chip and teases a 10-trillion-parameter model
At its Apsara Conference in Hangzhou, Alibaba introduced what it called China's most powerful AI chip (unnamed in the reporting available here) and said it's targeting an AI model scaled up to 10 trillion parameters, with chairman Joe Tsai reaffirming a full-stack push toward artificial superintelligence. No architecture, node, or performance figures for the chip were given in this coverage. SCMP
GUC announces 2nm, 16 Gbps HBM4E PHY and controller IP
Global Unichip Corp is offering design-ready HBM4E PHY and controller IP on a 2nm process at 16 Gbps per pin, aimed at customers building AI ASICs. It's an IP announcement, not a shipping product — the news is that 2nm HBM4E IP is now on the market for ASIC design teams to license. EE Times
r/FPGA engineers report unusually strong RTL generation results from Claude Opus 5.5
A thread titled "Opus 5.5 is insane at RTL" drew 137 upvotes and 74 comments on r/FPGA — a notably high engagement level for that subreddit. The post body wasn't available to check specifics against, so treat this as a community signal that a new model is drawing attention for RTL work, not a benchmarked claim. r/FPGA
A Reddit thread claims DRAM die cost has overtaken leading-edge logic on a per-area basis
A Tom's Hardware piece, linked from r/hardware (382 upvotes), reports that AI-driven memory demand has pushed DRAM die value per unit area past leading-edge compute silicon. The full article text wasn't accessible here to check the underlying figures, so this is reported as the publication's claim, not independently verified. r/hardware
Also noted
- GRADE-RTL evaluates LLM-generated RTL past compile success with five checks — port signature, elaboration, module completeness, and more — arXiv
- SLED-IFV uses solver-validated LLM decomposition to scale formal hardware information-flow verification past two recurring proof barriers — arXiv
- VSpector checks RISC-V CPU RTL directly against the official natural-language spec to find bugs, rather than relying on predefined test artifacts — arXiv
- WaveletECO pairs a closed-loop physical-ECO execution platform with a specialized local LLM for multi-round timing/electrical repair — arXiv
- Dynamic Slack-Aware Clocking replaces a fixed global clock with a proactive, per-operation timing margin for near-threshold TPUs — arXiv
- A droop-aware extension of the GridFM power-systems foundation model adds control-regime features so AC power-flow analysis isn't blind to operating mode — arXiv
- A circuit-architecture-training co-design framework uses sense-amplifier regeneration to skip SAR comparisons in analog compute-in-memory, characterized in 55nm CMOS — arXiv
- GPUThor, a Rowhammer attack from the University of Toronto, reverse engineers GPU memory-access coalescing to hammer ECC-protected NVIDIA GPUs with non-uniform patterns — Semiconductor Engineering
- SEMICON India 2026: five chip-packaging plants move into production as India's $13.5B ISM 2.0 program expands — EE Times
- Two small new open-source crates: reticle, a from-scratch VHDL/Verilog compiler in Rust with FPGA/ASIC backends, and chipsmith-cli, a command-line toolchain manager for Intel/Altera FPGAs — reticle · chipsmith-cli
- A MicroZed Chronicles walkthrough runs local AI models for RTL generation on real FPGA hardware — r/FPGA
- Bernstein estimates Huawei's Kirin 9050 Pro has narrowed the process gap with Apple's chips to about three years, from roughly four — SCMP
Landscape watch
- Form D: NonPublic Semiconductor Fund V, a Series of NonPublic Master, LP — SEC EDGAR
- Form D: Oxshott NP Semiconductor Fund IV, a Series of NonPublic Master, LP — SEC EDGAR
112 items considered: 31 RSS · 30 Reddit · 29 arXiv · 9 OpenAlex · 3 GitHub · 3 lab news pages · 2 crates.io · 2 Hugging Face · 2 SEC Form D · 1 HN · 0 conferences · 0 PyPI · 0 USPTO patents. No adapter failures. USPTO patents ran this week (last 2026-09-23) and matched nothing across its tracked assignees; SEC Form D matched the two funds above. Excluded as already covered: SiliconCompiler v0.38.9 (same release headlined 2026-09-21), CXMT's G5 manufacturing-platform story (same SCMP article headlined 2026-09-21), Hygon's datacenter-to-robotics expansion (same SCMP article, 2026-09-21 also-noted), the "every Nvidia GPU has RISC-V cores" Hacker News post (same thread, 2026-09-21 also-noted), and HeteroReason's FPGA-GPU speculative-reasoning artifact (same Zenodo record, 2026-09-11 also-noted). The iree 3.12.0 and TVM v0.27.0 release-candidate trains continue with no stable release yet and remain excluded pending one. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.