What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
A week of "how much should we trust a design agent" pieces lands at once, TSMC included
Semiconductor Engineering ran a cluster of pieces converging on the same question: as AI agents take on more of chip design, who decides what they're allowed to own, and how is that trust earned? One proposes explicit autonomy levels for design agents (L1 to L5, echoing the self-driving framing) — what a system can decide, the scope it owns, how its work gets validated, and who signs off when it can't. Another argues EDA's path forward runs through formal proof and auditable workflows, not just faster agents. A third looks at the coordination problem once agents span multiple design silos rather than working inside one tool. TSMC's own write-up of its Open Innovation Platform ecosystem describes a parallel push: an "AI Design Kit" for agentic workflows across its partner tools. None of these ship a product; together they're a foundry-to-EDA-press signal that agent trust, not agent capability, is the live design question right now. Autonomy Levels For Design Agents · When AI Agents Cross Chip Design Silos · EDA's Future Is Evidence-Driven Automation · Inside TSMC's Evolving Design Ecosystem
Two independent papers this week point LLMs at IC3/PDR, hardware verification's workhorse algorithm
IC3 (also called property-directed reachability, or PDR) proves safety properties by incrementally building an inductive invariant out of lemmas, and its effectiveness lives or dies on the heuristics that pick useful lemmas. Agentic-IC3 has an LLM search for semantic proof structure instead of operating on a bit-blasted, high-level-relationship-free representation. LLM4PDR does the same thing one level down, using an LLM to guide word-level PDR's search for proof-relevant bit-vector and array relations in datapath-heavy designs. Different entry points, same bet: that an LLM's sense of design semantics can unstick a search algorithm that's been stuck on low-level representations for two decades. Agentic-IC3 · LLM4PDR
TSMC starts A14 pilot production; Intel's own forecast puts 14A within 5% of it
r/hardware threads report TSMC has begun pilot production on its A14 node ahead of risk production next year, while Intel is reportedly forecasting its competing 14A node will land within 5% of A14's performance — a notably conservative number given Intel has also been touting 18A's frequency lead and promising 20% gains from 14A's backside power delivery. Neither post's underlying source article was accessible here to check the numbers directly, so treat both as reported industry claims rather than independently verified figures. Taken together they're the clearest public marker yet of how close Intel thinks it can get to TSMC's next leading-edge node. TSMC A14 pilot production · Intel 14A forecast
ETH Zurich graduate students design and open-source a full standard-cell library on IHP's open 130nm PDK
Standard-cell libraries sit at the boundary between transistor-level design and automated digital flows, but their design and characterization rarely get taught directly. ETH Zurich's VLSI 5 course has 19 students design, lay out, characterize, and integrate their own cells on IHP's open-source SG13G2 130nm PDK, and released the result as EZ130_8T — an open-source 8-track standard-cell library built by students rather than a vendor or research lab. It's a teaching artifact more than a competitive PDK entry, but it's one more usable library on an open process node. arXiv
ASML begins operations in India, tied to Tata Electronics' fab buildout
ASML has started India operations, with the move linked to Tata Electronics' fab expansion in the country. Details on scope (sales and support versus deeper technical presence) weren't accessible in what was fetched here, but a lithography-tool vendor establishing an India presence alongside a domestic fab customer is a concrete step in India's push to build its own semiconductor manufacturing base, distinct from the packaging-only capacity SEMICON India has been reporting all week. r/hardware
A CMOS-integrated MRAM Ising machine reports sub-nanosecond combinatorial-optimization steps
Two linked Nature Electronics papers — a primary report and an accompanying News & Views commentary — describe an Ising machine for combinatorial optimization built by integrating magnetoresistive RAM directly with CMOS, with the headline property being sub-nanosecond operation. No abstract text was accessible here beyond the titles, so treat this as a materials/device-level claim to watch rather than a verified benchmark against other Ising-machine approaches (optical, quantum-annealing, or other MRAM-based designs). Ising machine paper · News & Views commentary
Also noted
- RVVTS does open-source RTL bug hunting for complex RISC-V ISA extensions — r/RISCV
- RIVET is an open-source, Chisel-generated multi-rate Ethernet subsystem for RISC-V — r/RISCV
- Zamlet, an in-progress exploratory RISC-V vector processing unit — r/RISCV
- Open-source radiation hardening and fault injection work targets VeeR and Verilator — r/RISCV
- A WAL-based analysis digs into CVA6 branch prediction behavior — r/RISCV
- RISC-V hardware attack detection using on-chip hardware performance counters — r/RISCV
- RISC-V Manual Volume IV, covering debug and trace, is being prepared — r/RISCV
- Monte Cimone v3 checks in on where RISC-V stands in high-performance computing — RISC-V International
- pnsrouter, a new open-source crate, is an interactive push-and-shove PCB router inspired by KiCad's PNS router — crates.io
- Toki, released as open source, profiles HBM performance on FPGA systems by jointly accounting for RISC-V soft-core execution and host-DMA traffic over PCIe — arXiv
- A hardware-fuzzing SoK analyzes 52 fuzzers across RTL/IP, CPU, NoC, and SoC designs to frame verification as a bounded search problem — arXiv
- Edu4Chip reports lessons from bringing chip tapeout into university education across institutions with different curricula and infrastructure — arXiv
- An IEEE Computer piece pairs silicon photonics with rack-scale system design, framed as AI doing the matchmaking between the two — IEEE Computer
- Hot-cold tiering across HBM and high-bandwidth flash targets the idle-session memory problem in agentic LLM serving — arXiv
- A paper works through multi-kW power delivery methodologies for advanced 3D heterogeneous integration — arXiv
145 items considered: 39 arXiv · 39 Reddit · 36 RSS · 23 OpenAlex · 4 GitHub · 3 Hugging Face · 1 crates.io · 0 HN · 0 conferences · 0 PyPI · 0 lab news pages · 0 USPTO patents · 0 SEC Form D. No adapter failures. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-23 and aren't due again until 2026-09-30, so Landscape watch is omitted. Excluded as already covered: AgenticSizing, GRADE-RTL, SLED-IFV, Dynamic Slack-Aware Clocking, and HeteroReason's FPGA-GPU speculative-reasoning artifact (all headlined or also-noted 2026-09-23, resurfacing here with no material new development), the Alibaba 10-trillion-parameter-model/AI-chip story and the Huawei Kirin/Apple process-gap Bernstein piece (same SCMP articles, 2026-09-23), and the SEMICON India packaging-plants story (same EE Times article, 2026-09-23 also-noted). The iree 3.12.0 and TVM v0.27.0 release-candidate trains continue with no stable release yet and remain excluded pending one. A Hugging Face dataset matching the "eda" discovery query (zomato_delivery_EDA) is exploratory-data-analysis, not electronic design automation, and was excluded as off-topic. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.