What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
NVIDIA pushes AI-agent policy enforcement onto a DPU, and open-sources the software half
NVIDIA's Open Agent Safety Platform splits agent safety into two layers: OpenShell, an open-source runtime that sandboxes an agent's execution and checks its outbound requests against declared policies without modifying the agent, and Sentry, an enforcement layer running on a BlueField-4 data processing unit sitting on the network path between agents and the models/services they call. The actual design decision is where the enforcement point lives — on separate silicon rather than inside the same host the agent runs on — so a compromised or misbehaving agent can't reach the code that decides what it's allowed to do. OpenShell also claims formal verification of its own policies, meant to catch a rule that looks safe but accidentally grants more access than intended. Hacker News picked it up under a blunter framing: a watchdog chip for AI agents. NVIDIA: Open Agent Safety Platform · NVIDIA: OpenShell · Hacker News
Apache TVM cuts a stable v0.27.0, closing a release-candidate train this pulse has tracked since 2026-09-14
GitHub's API confirms the v0.27.0 tag published 2026-09-25 is a full release (prerelease: false), not another candidate — this pulse has excluded the rc20260907-onward train pending a stable cut across four prior briefs. The release itself is maintenance-weight: Relax/ONNX import fixes, deterministic Z3 context handling for the arithmetic layer, MSVC and CUDA/Metal backend fixes, and a new table-driven PTX dialect for NVRTC code generation. GitHub
Peregrino fits the entire Falcon post-quantum signature scheme on one low-end FPGA
Falcon is one of NIST's standardized post-quantum signature schemes, but its reliance on floating-point math has made it hard to implement in hardware — prior work covered only pieces of the scheme, or used high-level synthesis for a full implementation. Peregrino is a from-scratch HDL design of the complete scheme, including an emulated floating-point datapath for FPGAs without a native FPU, and fits entirely on a single Artix-7 XC7A200T. Against the one prior full implementation (HLS-based), it uses roughly 2x fewer LUTs and flip-flops, 2.7x fewer BRAMs, and 10x fewer DSPs — small enough to fit on one FPGA where the earlier design needed two. arXiv
BOLT formally checks that an ML compiler's accelerator mapping does what the source code says
ML compiler frameworks routinely offload code to accelerator-specific hardware intrinsics, but most don't verify the mapping preserves the original program's behavior — a mismatch that would surface as a silent wrong answer, not a compile error. BOLT is presented as the first framework for formally verifying these compiler-to-accelerator mappings against a hardware semantics, aligning software loop nests with the hardware and relating their data layouts to build a provably equivalent product program. The authors verified several complex mappings on two open-source ML accelerators as a proof of concept, not yet a production compiler pass. arXiv
PipeDRAM removes the data-transposition tax that's held back in-DRAM computing
Processing-using-DRAM techniques get bulk bitwise operations for free by exploiting DRAM's analog behavior, but they need data laid out vertically down a column — the opposite of the horizontal, cache-line-friendly layout normal memory systems use, so every operation pays a transpose cost. PipeDRAM reorganizes bits inside each memory request so operations run directly on horizontally laid-out data, then pipelines bit-dependent and bit-independent steps to recover the parallelism the reorganization would otherwise cost. The paper reports up to 11.8x higher performance and up to 38x lower energy against compared platforms — the authors' simulated numbers, not silicon. arXiv
EAAC tries to lower the cost of building a compiler for a new accelerator, not just the accelerator itself
Most accelerator projects treat the compiler and the hardware as separately owned problems, which is part of why full-stack integration is slow. EAAC is an MLIR-based compiler and hardware architecture meant as a blank, unopinionated starting point: it supplies just enough compiler machinery for data orchestration so a new accelerator can plug into existing MLIR frontends. The authors validate it with a systolic-array GEMM accelerator paired with a RISC-V core, reporting a 28x speedup over a RISC-V-only baseline on a synthetic fully-connected-layer workload — one prototype benchmark, not yet a general result. arXiv
Also noted
- CIRCT/firtool 1.160.0 ships AXI4 crossbar verification and datapath lowering improvements — GitHub
- OpenTPU, a learning-focused open FPGA AI accelerator project, runs Qwen 3.5 — r/FPGA
- RISC-V International previews a browser-based RISC-V ISA Explorer — r/RISCV
- Milk-V Meles boots openRuyi via EDK2 — r/RISCV
- Two linked papers characterize neutron-induced routing-delay faults on Zynq UltraScale+ FPGAs and build a digital-twin model to predict them — SEU/AXI paper · GRACIDIT
- TUM, UNIMORE, and Applied Materials compare A7 CFET and A10 nanosheet FETs from cell parasitics to chip reliability — Semiconductor Engineering
- New open-source crates: stackup-eda and stackup-eda-parser elaborate PCB stackup designs for import into PCB tools, pliron-circt is an MLIR-based compiler infrastructure for RTL generation, and ruvector-fpga-transformer-wasm adds WASM bindings for an FPGA transformer backend — stackup-eda · stackup-eda-parser · pliron-circt · ruvector-fpga-transformer-wasm
- Ken Shirriff reverse-engineers the Intel 8087's tangent algorithm and finds it's doing more than CORDIC — Ken Shirriff
- FASP folds security-verification cost into synthesis-time hardware/software partitioning for digital microfluidic biochips — DOI
- Heat-resistant silicon carbide JFETs fabricated on 6-inch wafers operate at 600°C, a step toward practical extreme-environment circuits — Tech Xplore
89 items considered: 44 Reddit · 19 RSS · 11 arXiv · 4 OpenAlex · 4 crates.io · 3 GitHub · 2 HN · 2 Hugging Face · 0 conferences · 0 PyPI · 0 lab news pages · 0 USPTO patents · 0 SEC Form D. The OpenAlex groups query hit a rate limit (HTTP 429) this run; the 4 OpenAlex items above are from the primary query only, not a "nothing new" result. The weekly landscape sources (USPTO patents, SEC Form D) last ran 2026-09-23 and aren't due again until 2026-09-30, so Landscape watch is omitted. Excluded as already covered: LLM4PDR (same arXiv paper headlined 2026-09-25, resurfacing with no material new development). The iree 3.12.0 release-candidate train continues (rc20260925) with no stable release yet and remains excluded pending one — its sibling TVM release-candidate train, tracked as excluded since 2026-09-14, ended this run with today's stable v0.27.0, headlined above. Reddit's r/chipdesign, r/Semiconductors, and most of r/FPGA this window were career/interview/homework threads, out of scope per this pulse's relevance rules; the two engagement outliers (a Korea chip-tax-revenue Reddit thread at 233 upvotes, a three-month EU hardware-pricing tracker at 22) were excluded as earnings/consumer-pricing coverage without engineering substance. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.