What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
DeepSeek open-sources six software modules for Huawei's Ascend AI chips
DeepSeek released six modules aimed at Ascend that, per SCMP, mirror its earlier open-source tools for Nvidia GPUs. The stated goal is an "independent and controllable" software stack that lets Chinese AI workloads run without Nvidia silicon. The report doesn't say how the modules perform on Ascend, so what's confirmed is the release and the intent, not that the software gap has closed. SCMP
BEHAVE gives hardware-design agents a correctness check that doesn't punish valid timing differences
Checking an agent's RTL against a reference cycle by cycle rejects designs that are correct but use a different latency than the reference. BEHAVE instead has the agent write the RTL and a separate executable behavior model, then checks both against a hidden golden behavior model using random and solver-guided stimuli. The same evaluator supplies verifiable reinforcement-learning rewards without needing reference RTL. The authors release BEHAVE-Train and BEHAVE-Eval, 600 human-reviewed specification-behavior pairs. It's a paper with a released benchmark, not yet an independently reproduced result. arXiv
MEGATRON pairs a phase-change-memory analog compute array with RISC-V digital cores in a 28nm edge SoC
The chip combines a 4Mi-cell PCM in-memory-computing engine with a digital RISC-V neural processing unit, fabricated in 28nm FD-SOI. The authors report 57.5 TOPS/W on the analog engine at 1.52 Mparam/mm² with 4-bit effective weights, against 3.5 TOPS/W on the RISC-V processors alone. Those figures are the authors' own and cover different parts of the chip, so they aren't an end-to-end comparison. arXiv
C2FPlace cuts macro-placement wirelength 17.8% against two search-based baselines
The method combines evolutionary search, which picks parents by tournament and rips up and re-places random macro subsets, with a fine-grained pass that moves critical macros off the coarse grid. On ISPD2005 it reports 17.82% lower HPWL than EGPlace and 17.86% lower than RollPlace on average. On ICCAD2025 it reports the best average ranking under the evaluated power, performance, and area metrics. The wirelength figure is for the benchmark suite, not a production flow. arXiv
APEC-Route guides analog routing with a neural parasitic-capacitance model evaluated during the search
Most analog routers check parasitics after routing. APEC-Route predicts capacitance with a small MLP while expanding route candidates, and adds analytical wire resistance. On four finalized 65nm layouts the extractor's geometric-mean relative error is 5.54–6.77% against a field solver, at 251–345 μs per query. It's compared on an OTA, a comparator, and a CDAC with fixed placement, so three blocks is the evidence base. ACM DOI
A Clash study finds some high-level HDL constructs cost almost nothing in area
Researchers built an unsigned bit-serial MAC unit in 16 configurations in Clash, the functional HDL, mixing low-level bit manipulation with high-level constructs, and compared synthesized area. They report that some high-level constructs have negligible influence on circuit size, which calls into question whether hand-tuned low-level code is worth the effort. One small design, one HDL: a data point, not a verdict. arXiv
Also noted
- AMD releases an "Agentic AI FPGA Assistant" (title only; no detail in the post we saw) — r/FPGA
- A Reddit post announces GSys LibreCore, an open-source configurable in-order/out-of-order multi-core RISC-V processor billed as agent-friendly — r/RISCV
- Apache TVM ships v0.27.0.post1, a single fix for low-precision, tensor-map, and cluster kernels in CUDA-host bundles — GitHub
- A 16→8 integer square root fits in 2 LUT6s, with a follow-up post reaching error ≤ 7 in 7 LUTs — part 1 · part 2
- An r/FPGA post reports 21 billion 256-bit prime-field elliptic-curve scalar multiplications per second on an FPGA — r/FPGA
- Mirath, a TCitH-based alternative to SLH-DSA, gets a cross-layer ASIC design study — arXiv
- fenolite, a new PyPI package, is headless, agent-first PCB design automation that generates, verifies, and exports KiCad projects from code — PyPI
- New crates: reticle, a from-scratch VHDL/Verilog compiler in pure Rust, and chipsmith-cli, an Intel/Altera FPGA toolchain manager — reticle · chipsmith-cli
- Semiconductor Engineering covers PCIe 8.0 over UCIe 3.0 for chiplet packages, and Caliptra's path from open-source root-of-trust to production — PCIe/UCIe · Caliptra
- Chips and Cheese examines the Snapdragon X2 Elite's system-level architecture — Chips and Cheese
- More Than Moore interviews Richard Ho, OpenAI's VP Hardware — More Than Moore
- Hardware-aware mapping for analog in-memory training and a polyhedral compiler for digital compute-in-memory both appear on arXiv — analog training · PolyCIM
- CXMT reportedly plans to favour domestic suppliers in a US$5.2b memory-capacity investment — SCMP
Landscape watch
- Form D: Apogee Semiconductor, Inc. (Texas) — SEC EDGAR
166 items considered: 51 Reddit · 40 arXiv · 35 RSS · 16 OpenAlex · 9 Hugging Face · 7 crates.io · 4 GitHub · 2 HN · 1 PyPI · 1 SEC Form D · 0 conferences · 0 lab news pages · 0 USPTO patents. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. The weekly landscape sources (USPTO patents, SEC Form D) ran today: patents returned no applications, and the one Form D filing is listed above. Excluded as already covered: the tt-metal v0.79.0 release-candidate train (rc4 today, no stable release yet). Reddit's r/chipdesign, r/Semiconductors, and most of r/FPGA this window were career/interview/homework threads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.