What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
OpenAI and Synopsys announce "GPT-Synopsys" for chip design
Synopsys published a press release on 2026-09-30 titled "OpenAI and Synopsys Announce GPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design." The item we saw is the Hacker News submission (186 points) linking to it, with no body text, so what's confirmed is the announcement and its framing, not what the model does, how it is deployed, or any results. Hacker News · Synopsys
A report counts 343 immersion DUV lithography tools in Chinese-owned fabs
Per SCMP, citing a late-September report from the Centre for Technology & Statecraft, Chinese-owned fabs had acquired an estimated 343 immersion DUV systems by early 2026. Former US officials quoted in the piece are urging Washington and its allies to end further exports. The count is a think-tank estimate, and the export ban is a call, not a policy. SCMP
Portable AppImages for Yosys, ABC, Netgen, OpenSTA and Surelog
A Reddit post (cross-posted to r/chipdesign and r/FPGA) offers prebuilt AppImages of five open-source tools, aimed at skipping source builds and outdated distro packages. It is a community packaging effort; the posts don't say which versions are bundled or who maintains it, so check before depending on it. r/chipdesign · r/FPGA
Chisel 7.16.0 and CIRCT firtool-1.161.0 ship
Chisel 7.16.0 preserves literals in Cat, adds a basic reimplementation of chiseltest's verify, and fixes a leak of DynamicContext state when an exception is thrown; it bumps CIRCT to firtool-1.159.0. Separately, CIRCT's firtool-1.161.0 preserves register initial values in the FIRRTL optimizer, adds core !sv.net<T> and !sv.var<T> types, and adds MOS switch primitive support in ImportVerilog. Routine releases from the two projects, not yet pinned together. Chisel · CIRCT
STELLA is a 16nm CGRA for the non-matmul parts of ML pipelines
Aimed at kernels like LayerNorm, GeLU, FFT and circular convolution, STELLA combines a fast configuration path, per-PE hardware loop control and an elastic pipelined fabric. The authors report up to 110 GOPS/mm² at 850 MHz and 4.84–7.14x effective kernel throughput over baseline CGRAs. Baselines and workloads are the authors' choice. arXiv
A hierarchical RL method builds routing and switch placement valid by construction
For joint routing and switch placement at the level of logical communication routes, the method starts from a minimal routing graph and grows it through switch expansion, placement and route refinement. Each step preserves routing validity, so the search only visits feasible configurations. The abstract gives no numbers we could check. arXiv
ZTA-Q is an open RISC-V platform for TFLite INT8 CNN inference
It runs TensorFlow Lite INT8 models on an Arty A7-100T at 83.3 MHz and exposes a configurable post-processing datapath for studying how approximations (reduced multiplier precision, shared shift scaling, simplified rounding) affect accuracy. Reported overheads are 26.3% LUTs, 12.6% registers and 150% DSPs. A small FPGA research platform. arXiv
Also noted
- Veryl v0.22.0 is released — r/FPGA
- FPGA/FCCM 2027 CFP deadline is expected in about 13 days (calendar milestone, not a live check) — isfpga.org
- Semiconductor Engineering argues LLMs let engineers move beyond RTL to a representation that expresses intent — Semiconductor Engineering
- Emergence AI is deploying "neuroformal AI" with fabless chipmakers aimed at yield and fab, test and packaging failures — EE Times
- An automated closed-loop pre-silicon verification framework for DDR5 and LPDDR5/6 memory controllers parses JEDEC timing from VIP databases — arXiv
- Argus uses an agentic LLM to localize OS-level CPU bottlenecks — arXiv
- U-Sonic is an open-source 8-channel ultrasound transmit IP in a 130 nm RISC-V SoC — arXiv
- Timing-driven logic remapping with local physical context — arXiv
- Structure-augmented LLMs for HLS pragma optimization — arXiv
- A survey of RISC-V and machine learning is shared on r/RISCV — r/RISCV
- Characterizing high-bandwidth flash for LLM serving — arXiv
- Chips and Cheese covers Qualcomm's Snapdragon X2 Elite system-level architecture — Chips and Cheese
169 items considered: 50 Reddit · 44 arXiv · 36 RSS · 18 OpenAlex · 4 GitHub · 2 Hugging Face · 1 HN · 1 conferences · 0 crates.io · 0 PyPI · 0 lab news pages · 0 USPTO patents · 0 SEC Form D. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Patents and Form D are weekly and weren't due today. Excluded as already covered: the tt-metal v0.79.0 release-candidate train, TVM v0.27.0.post1, OpenAI's Richard Ho interview, and the DeepSeek/Ascend modules. Most of Reddit's r/chipdesign, r/FPGA and r/Semiconductors items this window were career, interview and homework threads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.