What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
Backside clock meshes beat frontside ones by 45% on skew in a 2 nm OpenROAD study
The paper calls itself the first design-space exploration of clock meshes on the back of the wafer with backside power delivery. It uses OpenROAD on GT2N, a 2 nm nanosheet technology, across four benchmarks of 1,938 to 15,311 flip-flops, and checks every design point with transistor-level SPICE, since a cyclic mesh can't be evaluated by static timing analysis. Against an identical frontside mesh the authors report on average 45% lower skew, 25% lower sink slew, 4.5% lower power and 28% less frontside clock wiring. Four benchmarks on a research technology: a direction, not a signoff result. arXiv
Ampere open-sources its CPU pipeline visualizer and the event format behind it
The paper describes two pieces of Ampere Computing's internal performance tooling, now released as open source: "event streams," a simulator-output format that records microarchitectural activity as typed events linked by transaction relationships, and Catscan, an interactive viewer built on it. The point is to move from a symptom to the instruction, uop or memory transaction that explains it. Pipeline viewers are routine inside CPU teams and rarely public, so a documented format is the useful part. arXiv
Evidence-guided RTL repair works from a reproduced failing run and waveforms
The framework targets repository-level bugs that span files, modules and clock cycles. It reproduces the failure, localizes it using waveforms and a toolbox, then builds a coordinated patch and replays the same scenario to confirm the violation is gone. The authors report better results than the baseline on HWE-Bench; the abstract gives no numbers, so how much better is unknown. arXiv
A 16-chiplet torus MCM GPU is reported to scale well; the abstract cuts off at 2.40x
The study sweeps SMs per chiplet, chiplet count and inter-chiplet topology to see when disaggregation pays off in performance and energy. Its headline result is that a 16-chiplet torus with 256 SMs delivers a 2.40x gain. The text we have is truncated, so the baseline and the energy side are not confirmed here. arXiv
RAPID tries to make in-DRAM compute work with ordinary row-oriented data layouts
Existing processing-using-memory designs reorganize data into bit-serial, column-oriented form, which forces costly layout transforms whenever work moves between DRAM and a conventional processor. RAPID adds migration cells for movement between neighboring bitlines and inversion cells for in-array inversion, so computation can stay on row-parallel, bit-parallel data. It is an architecture proposal; the numbers were cut off in our copy. arXiv
OpenC6 v2.0 adds hardware PMP isolation and U-mode execution on an ESP32-C6
The Reddit post describes a release for the ESP32-C6's RV32IMAC core with hardware PMP isolation, unprivileged U-mode execution, and an out-of-band LP-Core supervisor. The post carries no body text we could read, so what's confirmed is the title's claim and nothing about adoption or testing. r/RISCV
MIPS says its collaboration with Chinese firms on RISC-V is at an unprecedented level
Per SCMP, a senior MIPS executive says the US IP provider is working with Chinese companies more than ever as RISC-V adoption grows, despite the wider chip rivalry. It's an executive's own account in one article, with no specifics in the part we saw. SCMP
Also noted
- fastroute is a Rust port of Freerouting, an open-source PCB autorouter for KiCad and Specctra DSN, with length matching and controlled impedance — GitHub
- SiCo is a Codex-CLI-based assistant for custom IC design, from a project called opencad-abu — GitHub
- Jane Street publishes results from its ASIC puzzle — Hacker News · Jane Street
- Qualcomm licenses patents on Huawei's LogicFolding chip technology, per an r/hardware thread — r/hardware
- HeteroReason splits speculative reasoning across an FPGA draft engine and GPU reward and target models; the artifact includes a hardware simulator — Zenodo
- CONFERM does recurrence-aware temporal mapping for multi-cycle, multi-context CGRAs — arXiv
- Duplication-aware retiming for superconductor circuit minimization — arXiv
- Infineon and TU Munich on abstraction and validation from physical devices to RTL models — Semiconductor Engineering
- Semiconductor Engineering's weekly review lists autonomous workflow design, CFETs beyond 10 angstroms and a Spectre-v2 variant aimed at JIT compilers — Semiconductor Engineering
- NVIDIA ships DOCA agent skills for building BlueField applications — NVIDIA
- MICRO 2026 proceedings are expected in 12 days (calendar milestone, not a live check) — microarch.org
88 items considered: 34 Reddit · 18 arXiv · 15 RSS · 6 GitHub · 5 OpenAlex · 4 HN · 4 Hugging Face · 1 crates.io · 1 conferences · 0 PyPI · 0 lab news pages · 0 USPTO patents · 0 SEC Form D. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Patents and Form D are weekly and weren't due today. Excluded as already covered: GPT-Synopsys, the DUV tool count, CIRCT firtool-1.161.0, IREE 3.12.0 and its release candidates, and the tt-metal v0.79.0 release-candidate train. Most of Reddit's items this window were career, interview and homework threads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.