What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
SparseCraft lets an LLM edit Gemmini's Chisel RTL, with every candidate simulated, checked bit-for-bit and synthesised
The loop runs 15 iterations. In each one the model reads the measured result of the last, then edits the Chisel RTL, memory configuration and sparse-kernel schedule of a Gemmini accelerator through MCP tool servers. No candidate counts until it passes a legality check, elaboration, cycle-accurate simulation, a bit-exact comparison against a golden reference on every output, and synthesis. On one 512×512 GraphChallenge sparse-DNN layer the authors report 2.1x fewer cycles, 9.8x less off-chip traffic and 22.8% less area than a block-sparse Gemmini baseline. A single layer and a single baseline, but the gating is the interesting part: the model is judged on measurements, not on a cost model. arXiv
vTen replaces cocotb's fine-grained sync with kernel-granular batching for accelerator verification
The problem is the gap between tensor-level software models and signal-level testbenches. cocotb synchronises with the simulator at fine grain, which the authors say is prohibitively slow for accelerators. vTen describes verification intent in a declarative DSL and batches work per kernel, so host and simulator talk far less often. On a production-scale 3D U-Net accelerator they report 2x lower simulation latency and 60.3% less testbench code than cocotb. One design, by the authors; worth a look if you drive accelerator testbenches from Python. arXiv
Alkaid is an open-source compiler from sub-microsecond dataflow kernels to RTL or HLS-ready code
It targets the same ultra-low-latency ML pipelines as hls4ml, plus the pre-processing, post-processing and control logic around them. An arithmetic-centric IR keeps fixed-point semantics and per-operation bitwidths, and an analytical performance model lets you explore the design space without running synthesis. Across MLPs, GNNs and transformers the authors report 20–30% lower LUT usage than the best prior flows for bit-exact equivalent designs, and up to 40% lower latency in some cases. arXiv
SiliconCompiler 0.38.10 stops defaulting remote runs to a public server
The one breaking change: a remote run now fails unless a server has been configured with sc-remote. The rest is plumbing, including gitlab:// and s3:// data roots, credentials masked in logs, run manifests and sc-issue testcases, and nested -f/-F file lists in Design.read_fileset. If you have scripts that relied on the old default, they will break on upgrade. Release notes
Trinity trains a flow-matching floorplanner on the same differentiable terms its refiner optimises
Diffusion floorplanners usually train on reference layouts and leave constraints to guidance and a legalizer. Trinity uses six differentiable functions for the objectives and constraints as the training loss, the energy of a closed-form refiner after sampling, and a soft cost for scoring each stage. The authors re-implemented four prior diffusion placers under one recipe on FloorSet to compare them. They report a refined soft cost 36% below the best ported pipeline and a mean hard cost of 1.014 at 1.63 s per case. They also find the refiner decides more of the final cost than the generator does. arXiv
CACHEFORGE evolves cache-replacement policies by putting an LLM in a simulator loop
Each iteration the model proposes new C++ replacement logic, and a CRC-2 ChampSim trace simulation evaluates it. Reward shaping, structural checks, mutation and cross-policy crossover keep candidates within hardware limits. The authors say it beats all CRC-2 baselines across SPEC CPU2006 and yields compact policies. Trace-based results on one benchmark suite, so treat the hardware efficiency claim as unproven until someone builds one. arXiv
Meta reports 12x less unplanned downtime from its in-house multi-host NIC, fbnic
The paper is about operating the chip, not designing it. Vendor multi-host NICs retrofitted from single-host designs shared firmware and buffers, which the authors say caused cascading isolation failures over seven years. fbnic isolates hosts physically, and the hyperscaler takes on the ops work: hardware-in-the-loop CI across firmware, driver and kernel, a driver-first design with fewer than ten firmware message types, and scoped repair automation. Over ten months they report a 12x drop in unplanned unavailability and 2.3x fewer hardware swaps than vendor NICs on the same platform. arXiv
Also noted
- Chipstrat's "Is EDA Dead?" takes up whether model labs can replace EDA tools, following GPT-Synopsys — Chipstrat
- Kepler says it will have a 3D ferroelectric memory in production in 2027, claiming 5–10x better bandwidth per watt than HBM (company claim) — EE Times
- Terracotta, a flexible DRAM interface and memory controller, aims to make new DRAM techniques adoptable without custom hardware — arXiv · Semiconductor Engineering
- gem5-CIMD is a full-application computing-in-DRAM simulator on current gem5, with sixteen CIM instructions — arXiv
- VHDL-REPOBENCH is a repository-level LLM benchmark of about 100 open-source VHDL repositories with self-verifying testbenches — arXiv
- A high-level synthesis flow generates asynchronous circuits from imperative programs on the AHIR framework — arXiv
- Exact realizability cuts connect useful-skew scheduling to discretely tunable clock trees; the authors flag cases where it loses to monolithic optimization — arXiv
- STEP-KD distills post-routing timing knowledge down to a post-synthesis predictor — arXiv
- Ferrite Lithic is a Rust-native hardware DSL with a cycle simulator and Verilog generator, shown on r/FPGA — Reddit
- A Reddit post says a RISC-V chip with a matrix accelerator was designed using only open-source tools (title only) — Reddit
- PACE is a small in-order RV64GC core with scout-based pre-computation, shown on r/RISCV — Reddit
- The US finalized up to $1 billion in CHIPS R&D funding for Anderon, a quantum foundry IBM established this year — IEEE Spectrum
- Chips and Cheese examines the core in NVIDIA's Olympus server CPU — Chips and Cheese
- iree-3.13.0 release candidates continue the nightly train — GitHub
137 items considered: 51 arXiv · 37 Reddit · 29 RSS · 9 OpenAlex · 5 Hugging Face · 4 GitHub · 1 HN · 1 SEC Form D · 0 conferences · 0 PyPI · 0 crates.io · 0 USPTO patents · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Patents and Form D are weekly and weren't due today; the one Form D item was already covered on 2026-09-30. Excluded as already covered: backside clock meshes, RAPID, HeteroReason, GPT-Synopsys, and the tt-metal v0.79.0 release-candidate train. Most of Reddit's items this window were career, interview and homework threads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.