What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
An EDA group ran eight agent-driven research trials and asks how the field will validate results that are easy to produce
One faculty member and seven students, some with no publication experience, let agents develop mathematical constructions, analyze existing tools and implement improvements on topics outside their depth. Some efforts fell short of their practical goals. The authors also used AI to classify 8,420 papers from four EDA conferences and two journals (2022–2026) and report that 97.7% of 2,380 primary-core papers are computationally closed, meaning a program can check them. Their argument is that much of EDA is an executable environment for agents, and the open question is how venues validate and reward work that is cheaper to produce than to examine. A case study with a small cohort, but it comes from people inside the field. arXiv
mqt-scpd is an open-source, fully automatic layout flow for planar superconducting quantum chips
Layout for these chips is still mostly done by hand, taking days or weeks even for moderate designs, and earlier automation relaxed physical constraints enough that the results weren't fabrication-ready. The authors formalize the device physics as a geometric problem, then run geometry-aware partitioning, ILP-based port assignment and hierarchical routing. They report manufacturing-ready, design-rule-clean layouts in seconds to a few minutes, up to 25x faster than the state of the art on complex instances. The tool is released as open source as mqt-scpd. arXiv
CacheFit puts circuit-level cost inside an LLM search for cache replacement policies
Policies are normally chosen for IPC in simulation and trimmed in RTL later, after the algorithm is fixed. CacheFit connects ChampSim to HARCOM, a circuit-level cost model, and has a language model propose variants that are scored on latency, area, power and speedup while the algorithm is still being written. Applied to MPPPB, the most expensive baseline in power and transistors, it produces Fit-MPPPB with 60.3% less storage and 56.3% less static power. The abstract cuts off after that, so the remaining numbers aren't available here. Similar in spirit to CACHEFORGE (briefed 2026-10-07), with cost in the objective rather than as an after-the-fact check. arXiv
TraceDSE feeds execution traces, not just latency and energy, to an LLM critic for edge-SoC design exploration
Most design space exploration returns only aggregate metrics, including the recent LLM-guided versions. TraceDSE runs a proposer-critic loop in which the proposer suggests workload-to-processing-unit mappings and PU configurations (active cores, frequency), and the critic uses programmatic trace-analysis tools to find bottlenecks and suggest targeted changes. The target is joint mapping and configuration on heterogeneous CPU/GPU/NPU SoCs under latency and energy limits. The excerpt we have doesn't include the headline results. arXiv
RFChipAgent chains LLM agents through analog/RF design, from document retrieval to simulator-in-the-loop sizing
The flow covers retrieval over engineering documents, topology selection, schematic and testbench assembly, and a sizing engine that combines TPE and CMA-ES with every candidate simulated. A trust-scored database of verified results feeds later trials, all under human supervision. It is demonstrated on GF22FDSOI 60 GHz wideband mm-wave LNA topologies. "First of its kind" is the authors' claim, and the validation is one circuit family. arXiv
BenchmarkAnything uses agents to turn open-source repositories into simulator-ready benchmarks
The authors argue that tuning cores against a few tens of SPEC workloads overfits architecture research. Stripping real software into the clean binaries a simulator needs is what makes large suites impractical, so they have agents do it autonomously and say they harvested hundreds of applications from public repositories. Worth watching if you evaluate microarchitecture changes; the excerpt doesn't say how well the generated workloads match the originals. arXiv
SUSpMV, a sparse matrix-vector accelerator written in the new HDL SUS, is reported 79% faster than prior work on an Alveo U280
It uses all 32 HBM channels at 400 MHz feeding 32 compute units, with vectors kept in DDR so they don't compete for HBM bandwidth. The authors credit SUS's latency counting and inference for making very deep pipelines manageable. They report a 144.9 GFLOPs peak (94% of theoretical) against 98 GFLOPs for prior work on the same platform. One platform, by the language's own authors. arXiv
Magic 8.3.685 makes the Tcl event loop usable in its WebAssembly build
The tag carries one change: pull request #563 fixes the Tcl event loop in the WASM build and corrects the arguments passed to Tcl_DoWhenIdle(). Small, but it is movement on running the layout editor in a browser. Release
Also noted
- A survey of LLM-integrated hardware verification covers SVA generation, testbenches, bug localization, repair and formal; it warns that passing available checks doesn't establish the design intent is captured — arXiv
- ATLAS applies topological data analysis to Bayesian-optimization transistor sizing, tested on four analog benchmarks in GF180 and SKY130 — arXiv
- X-OPM builds on-chip power meters from tree-based feature engineering plus linear models, reporting R² > 0.93 on a C906 vector processor with under 0.1% area overhead — arXiv
- A framework adds RISC-V instruction extensions for compact transformer inference, reporting up to 2.19x speedup on the Synopsys trv32p3f core — arXiv
- Frontgrade Gaisler GR801 is a space-grade radiation-hardened RISC-V SoC based on the NOEL-V RV64GC core, posted on r/RISCV — Reddit
- A post shows the open-source Project Apicula toolchain running on the Tang 168k (title only) — Reddit
- Microchip Technology acquires VORAGO Technologies, per a post on r/Semiconductors (title only) — Reddit
- texo-flow, a new crate, orchestrates EDA flows with verification gates for Texo — crates.io
- rtl-coder-1.5b-gguf is a new small RTL-oriented model on Hugging Face, with no downloads yet and no description — Hugging Face
150 items considered: 56 arXiv · 43 RSS · 33 Reddit · 10 OpenAlex · 5 GitHub · 1 HN · 1 Hugging Face · 1 crates.io · 0 conferences · 0 PyPI · 0 USPTO patents · 0 SEC Form D · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Patents and Form D are weekly and weren't due today. Excluded as already covered: SiliconCompiler 0.38.10, the tt-metal v0.80.0 and IREE 3.13.0 release-candidate trains, "Is EDA Dead?", Anderon, Kepler and NVIDIA's Olympus core. Most of Reddit's items this window were career, interview and homework threads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.