What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
TPCS reports 36–42x over parallel Verilator by modeling RTL as transaction-pruned function calls
Cycle-level simulators are fast but loose; RTL simulation is exact but slow. TPCS tries to sit between them with one abstraction that covers microarchitecture modeling, cycle-accurate simulation and synthesizable RTL. Combinational logic becomes transaction-based function invocations, and host CPU control flow prunes the inactive logic, so there is no event scheduling or signal tracking. The authors report 36x–42x over parallel Verilator on SMP systems and 3.4x–7.2x over single-threaded Verilator on accelerators, with cycle-level waveform agreement on the traces they evaluated. Generated RTL lands within -4.7% to +2.6% of handwritten clock period and -3.3% to +4.0% on area. Author-run numbers on selected designs, but the claim is checkable against Verilator. arXiv
Anechoic, an FPGA Ising machine, removes the "echo" that makes dense Max-Cut annealing undo its own flips
On the 2,000-node K2000 Max-Cut benchmark, the authors find that two-thirds of flips in parallel stochastic annealing reverse the same spin's flip one step earlier. They treat this as an Onsager reaction from mean-field theory and subtract it, at the cost of one population count per step. Twelve engines at 250 MHz on an AMD Alveo V80 reach a cut of at least 33,000 with 99% probability in 0.05 ms, which they put at 5.2x faster than the fastest published hardware, at 5.4 mJ per solution. One benchmark family and one board; the speed comparison is the authors' own. arXiv
CacheFlex lets software turn part of a private L2 into scratchpad, with 2.02% area overhead post-layout
L1 capacity limits wide vector units, and L2 is an order of magnitude larger but invisible to software. CacheFlex adds a small ISA extension so software can convert part of L2 into scratchpad and control placement and lifetime, and it integrates with an out-of-order pipeline, memory consistency and OS context switches. The area figure is relative to the L2 in a 12 nm post-layout implementation. Performance comes from gem5 on an Armv8-A SVE prototype: kernel geometric-mean speedup grows from 1.12x to 1.44x, and memory-subsystem energy savings from 26% to 40%, as vector length scales from 512 to 2048 bits. Simulated speedups, not silicon. arXiv
Best Match plans hybrid-row-height placement and reports 91.8% lower post-route TNS than a commercial tool's uniform rows
Hybrid-row-height designs mix placement rows of different heights to trade power, performance and area. Best Match picks the row configuration that disturbs the timing-optimized initial placement least after legalization, now accounting for horizontal as well as vertical displacement, precise row positioning and macro blockages. Against a flow-based method it reports 48.4% less cell displacement and 68.8% less post-route total negative slack; against a commercial tool's uniform hybrid rows, 27.4% less routed wirelength and 91.8% less TNS. The comparison baselines are the paper's choice. DOI
Ubuntu now ships official desktop images for RISC-V
Per a Hacker News link to OMG! Ubuntu, Canonical has official desktop ISOs for RISC-V. The excerpt we have is just the link, so board support and requirements aren't available here. It is still a step for RISC-V being a machine you can install a mainstream desktop on rather than only a server target. Hacker News · OMG! Ubuntu
CXMT says it has made "key progress" on a 4F² memory cell, with a server-memory product planned by end of 2026
The Chinese memory maker described a new cell architecture aimed at higher density, one that Samsung and SK Hynix are also pursuing, according to a company statement reported by SCMP. President Cao Kanyu said a product based on it is planned by the end of 2026. It is a company claim made at an industry event, with no yields or specifications in what we have. SCMP
Semiconductor startups raised $8.5B across 80 companies in Q3
Semiconductor Engineering's quarterly tally puts the haul at $8.5B, with the large rounds going to companies working on data movement and memory. That is all the excerpt gives; the list of companies isn't included here. Semiconductor Engineering
Also noted
- VortexSynth uses profile-guided kernel reconstruction and an agent to port closed-source GPU workloads to Vortex, an open-ISA GPGPU; all active kernel pairs passed output-equivalence checks — arXiv
- A study of hardware malware detectors on FPGA and open-PDK ASIC finds tree- and rule-based classifiers use nearly an order of magnitude less area than function-based ones — arXiv
- Characterizing CPU-GPU memory sharing over unified memory architecture, title only — arXiv
- SILICON is a new open-source digital circuit simulator in C++ and Qt, posted on r/FPGA (title only) — Reddit
- virtual-bus is a new crate for testing embedded Rust drivers against register maps and RTL simulation, with virtual-bus-build turning Verilog into a Verilator model — crates.io · crates.io
- fairchild-osdi is a new crate loading Verilog-A models compiled by OpenVAF through an OSDI v0.4 runtime — crates.io
- Samsung's 2nm foundry yield is reported near 60%, per a post on r/hardware (title only) — Reddit
- A hobbyist's from-scratch RISC-V microcontroller computes pi to 1500 digits, posted on r/RISCV — Reddit
- HPCA 2027 notification is expected in about 13 days — HPCA
90 items considered: 30 Reddit · 18 RSS · 14 arXiv · 13 Hugging Face · 5 OpenAlex · 5 crates.io · 2 GitHub · 2 HN · 1 conferences · 0 PyPI · 0 USPTO patents · 0 SEC Form D · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Patents and Form D are weekly and weren't due today. Excluded as already covered: the tt-metal v0.80.0 and IREE 3.13.0 release-candidate trains. Most of Reddit's items this window were career, salary and interview threads, and the Hugging Face items were new low-signal Verilog datasets and fine-tunes with little or no downloads, out of scope per this pulse's relevance rules. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.