What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
An LLM agent designed an 11-bit SAR ADC on SKY130 to DRC- and LVS-clean, post-PEX spec, with a caveat about false passes
A paper on "vibe tapeout" for analog measures how far LLM agents get when they write their own schematic and layout generators, run EDA tools, read the results and fix the design. On the open SKY130 PDK, a cloud agent designed an 11-bit, 5.12-MS/s SAR ADC from its specification, produced DRC- and LVS-clean macros and met spec after parasitic extraction. Given a sanitized reference derived from the authors' 65 nm design, it reached signoff without human intervention with 1/1.6 to 1/2.8 the area of the no-reference runs. The agents also sometimes reported false passes, and the authors say verification independent of the design agent was essential. A second experiment on a commercial PDK is under NDA; one ADC, author-run. arXiv
Columbia and Google paper rethinks EDA infrastructure for agentic verification, aimed at RTL waveform analysis and debugging
Semiconductor Engineering summarizes a Columbia, Google DeepMind and Google paper, "Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification." The excerpt we have covers only the framing: verification workflows remain manual despite what LLMs can do. Results aren't in what we have, so this is a pointer to read, not a finding. Related on the open side, a new GitHub project, verdi_bridge, connects AI agents to a live Synopsys Verdi session over MCP for waveforms, signal values and driver tracing (20 stars, new). Semiconductor Engineering · verdi_bridge
A study of RTL-generation evaluators finds a generic cell-count metric reports unsupported improvement on 6 of 12 design pairs
The paper treats the evaluator as an experimental variable. It freezes candidate pairs and changes only the requirement profile, meaning security rules, protocol obligations, target context and provenance. In a preregistered pilot of six designs, twelve pairs and 72 decisions, the generic cell-count evaluator claimed improvement the matched evaluator didn't support in 6/12 pairs (Wilson 95% interval 25.4 to 74.6%). The matched evaluator caught all twelve injected regressions. Small pilot, but it is a reminder that RTL-generation scores depend on what the grader checks. arXiv
Formal reachability plus Bayesian optimization closes last-mile coverage bins on OpenTitan AES
The workflow maps each remaining coverage bin to existing testbench knobs using AST parsing and cone-of-influence tracing. It then uses formal proofs of unreachability to drop dead targets, groups what's left by formal difficulty and runs Bayesian optimization per group, all under a matched 20-simulation budget against constrained-random and random search. It closes bins in an existing human-written coverage model rather than inventing new verification goals. The excerpt cuts off before the full OpenTitan results, so read the paper for the numbers. arXiv
Yosys 0.70 adds a constant-multiplier pass, optimization barriers and colored terminal logs
New in the release: an mcm pass that replaces constant multipliers with shared adder graphs, an experimental optbarriers pass with -barriers on flatten and prep, -macc-only for alumacc, -purge for rmports and -select for ltp. The read_xaiger2 pass is removed, which matters if a script calls it. Release notes only; no benchmarks of the new passes. GitHub
LizTail splits a 128×128 systolic array into 32 segments to keep PEs busy on skinny matrices and small-batch decoding
Fixed 2D systolic arrays leave processing elements idle on skinny matrices, small-batch autoregressive decoding and operators with independent partitions. LizTail adds constrained reconfiguration at predefined 128×4 segment boundaries, aiming to cover both shape adaptation and spatial parallelism without the interconnect and control cost of fine-grained routing. The excerpt doesn't include the utilization or area results. arXiv
GarageWorks runs one cocotb testbench against both software RTL simulation and an FPGA
The lightweight framework hides backend interfaces behind a shared abstraction and uses synthesizable AXI dispatchers for DUT-specific control on the FPGA. It is validated on AMD Alveo V80 boards with several internal designs, is meant for standalone designs and sensor processing logic rather than full SoC prototyping, and has initial support for AI-assisted test-component generation. arXiv
Applied Materials opens a $5B R&D center in Sunnyvale as ASML says it can't fill AI chip-tool orders through 2028
Applied Materials unveiled its EPIC Center on 12 October, a facility meant to put chipmakers, equipment suppliers and researchers in one place for R&D and commercialization. Separately, a Reddit post reports ASML cannot fill AI chip-tool orders through 2028 and has lifted guidance a third time, and EE Times notes ASML's EUV expansion depends partly on Zeiss's precision-optics output. Equipment capacity is the constraint behind much of what builders can get fabbed. Reported figures are from the outlets' summaries. EE Times · IEEE Spectrum · EE Times (Zeiss) · r/Semiconductors
Also noted
- Characterization of HBM power consumption on real HBM2 chips (ETH Zurich, NYU), first comprehensive experimental study per the authors — Semiconductor Engineering
- OpenTPU: a "hop in, we are building OpenTPU" call for contributors, title only — r/chipdesign
- YesOS, a from-scratch RV64GCV OS running in M-mode with a PMP layout proven with Z3 at every build, QEMU only so far — r/RISCV
- "The state of agentic AI in chip design tools in 2026," discussion thread, title only — r/chipdesign
- GlobalFoundries selected to operate two new fabs in New York under a U.S.-Japan initiative — r/Semiconductors
- SkyWater and D-Wave extend quantum manufacturing collaboration through a multi-year agreement — r/Semiconductors
- Stateless stochastic computing for generative AI on superconducting logic, a model-hardware co-design — arXiv
- PRIM: energy- and endurance-aware compiler optimization for digital compute in non-volatile memory — arXiv
- Programmable data layouts via on-the-fly data transformation — arXiv
- SafeDSE: joint exploration of safety architecture patterns, mapping and scheduling for dataflow applications — arXiv
- Chinese chip exports rose 136% year on year in September to US$45B — SCMP
- Ledger confirms a hardware-wallet spy implant behind crypto thefts — Hacker News
- NVIDIA Run:ai is now open source — NVIDIA
- ironaccelerator-fpga, a new crate for an AMD/Xilinx Alveo and Versal backend via XRT, enumeration and probe only — crates.io
Landscape watch
- Form D: Finwave Semiconductor, Inc., matched on keyword "semiconductor" — SEC EDGAR
109 items considered: 34 arXiv · 32 RSS · 30 Reddit · 6 GitHub · 3 OpenAlex · 2 crates.io · 1 HN · 1 Hugging Face · 1 SEC Form D · 0 PyPI · 0 conferences · 0 USPTO patents · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed), so its zero is not a "nothing new" result. Excluded as already covered: the tt-metal v0.80.0 and IREE 3.13.0 release trains. Most of Reddit's items this window were career and interview threads and were out of scope. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.