What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
A coverage-closure agent takes three small designs to 100%, with data integrity checked outside the model
LLM agents can close functional coverage, but coverage only shows a state was reached, not that the data on the way there was correct. This paper reads coverage from the simulator's own cocotb-coverage report rather than from the model's account, and checks data with scoreboards separate from the model. On an async FIFO, a UART transmitter and an AHB2APB bridge, coverage went from 91.7%, 88.9% and 67.4% to 100% within an 8-iteration budget in every logged run. The authors list the weaknesses themselves: three designs, no baseline, no ablation, runs from several agent checkpoints, and the scoreboard monitor is not yet attached to the LLM-generated tests. It lines up with the false-pass caveat in Wednesday's SAR ADC paper: the grader has to sit outside the agent. arXiv
Meta reports up to 1.5x training throughput on AMD MI350X over a direct CUDA port, and upstreams the work
Meta runs NVIDIA GPUs, AMD GPUs and its own MTIA parts, and this paper describes porting recommendation-model training to AMD Instinct MI350X, using NVIDIA B200 as the comparison. It argues for revising model structure to use the MI350X's 1.6x HBM capacity instead of porting directly, an analytical model that picks kernels without warm-up tuning, and agentic workflows to ease the CUDA-to-ROCm move. Against the directly ported baseline it reports up to 1.5x end-to-end throughput, and says the contributions went upstream to PyTorch, Triton and ROCm. The authors call it the first hyperscaler report on productionizing AMD GPUs for large-scale training. Single company, one model family. arXiv
An application-specific RISC-V for FPGAs closes timing at 775 MHz in 170 ALMs, at the cost of binary compatibility
The paper builds a deeply pipelined RV32 core that runs above 700 MHz on a mid-range device, then compiles the application binary and a specialized core together. Each instruction gets an application-specific encoding and unused datapath and decode logic is removed during synthesis. The smallest result is 170 ALMs closing at 775 MHz on an Altera Agilex-5. The cores stay assembler-compatible with the original program but are no longer binary-compatible with general RISC-V, and the authors show they can be packed into deterministic areas and stepped-and-repeated. Results are for RV32I, RV32M and RV32F example designs. arXiv
NVIDIA publishes a NeMo Gym write-up on agent reliability and tool-calling efficiency for chip design
The developer-blog post starts from the problem that chip-design agents produce plausible but incorrect artifacts. The excerpt we have covers only that framing, so we can't say what NeMo Gym measures or what it reports. A pointer to read, not a finding. Related: Semiconductor Engineering has an interview with Synopsys CEO Sassine Ghazi on how close fully autonomous chip design is, again with only the teaser in hand. NVIDIA · Semiconductor Engineering
TALU replaces a RISC-V core's single ALU with a grid of ALU tiles and reports 1.8–5.5x over a vector core
TALU is a 5-stage core whose execute stage is an NxN grid of registered ALU tiles. Operands route only forward between neighbours, with diagonal forwarding so reductions collapse spatially, and a small custom extension configures each tile. On the RISC-V2 vector processor's benchmark suite it is 1.8–5.5x faster than RISC-V2 and 4.5–15.5x faster than Vicuna at equal lane count. A retimed version places and routes at 1.03 GHz in 45 nm and 0.30 mm², half the area of RISC-V2. A paper result, in an academic 45 nm flow. arXiv
MFSA folds block scales into the running sum to cut microscaling overhead by about two thirds
The multi-format systolic array uses dot-product-accumulator PEs extended from an open-source trans-precision FPU, covering FP32 down to FP4 and INT4 on a shared datapath. Online Block-Scale Rebasing applies each block's scale to the FP32 partial sum at block boundaries, avoiding a second accumulator. In TSMC 28 nm at 1 GHz the authors report 64.2% less area and 67.5% less energy than a naive MX implementation, and a routed 16x16 array reaching 0.5/1/2/4 TOPS for FP32/BF16/FP8/FP4, with no loss of numerical stability on real LLM traces. arXiv
Japan's reported $21B offer to GlobalFoundries would fund two New York fabs; TSMC confirms Texas talks with Musk's Terafab
EE Times puts a figure on the GlobalFoundries arrangement we noted Wednesday: a $21B Japanese offer to add two New York fabs and lift U.S. chip capacity about 10%, with analysts warning about reliance on state support. Separately, TSMC chairman C.C. Wei said on the earnings call that TSMC is discussing a role in Elon Musk's proposed Terafab in Texas, but that any partner plant "has got to be run by TSMC." Both are talks and offers, not signed projects. EE Times · SCMP
SiliconCompiler 0.38.11 removes sc-dashboard and sc-server, adds sc-config and a run listener
The Major item is breaking: sc-dashboard, sc-server and the cleanup app are gone in favor of python3 -m siliconcompiler.apps.utils.dashboard, python3 -m siliconcompiler.remote.server and sc-config cache clean. New: sc-config for settings, cache and file locations, --gui/--web/--shell on a node's replay.sh, a RunListener via Scheduler.add_listener (TaskScheduler.register_callback is deprecated), and opensta in the sc-install ASIC groups. Also out: CIRCT firtool-1.162.0, with PyCDE and ExportVerilog changes including sv.package.extern for externally defined packages. GitHub · CIRCT
Also noted
- Helix, an FPGA Krylov-solver accelerator with a DSL compiler, up to 7.91x over Xilinx XcgSolver on an Alveo U55C — arXiv
- Foundations of hardware-software leakage contracts, a survey of the ISA-level side-channel abstraction — arXiv
- PAGE404: breaking GPU isolation on Grace Hopper through hardware-assisted page migration — arXiv
- Parallel sparse outputs for tensor compilers — arXiv
- Compiling multi-threshold operators for quantized activations in custom DNN accelerators — arXiv
- Bolt Graphics test chip demo, EM simulation in hardware, video only — r/RISCV
- SpacemiT K3 Pico ITX boots openRuyi Creek with EDK2 UEFI; SpacemiT has a launch at RISC-V Summit China in three days — r/RISCV
- Debian riscv64 with KDE Plasma in a browser tab via a riscv64-to-WebAssembly JIT — r/RISCV
- Alibaba DAMO's Jianyi Meng on an on-chip AI milestone for RISC-V — RISC-V International
- ASML is expanding into hybrid bonding, with 27 patent families filed Dec 2022–Nov 2024, per a research-firm report — SCMP
- A Chinese start-up unveils a prototype EUV light source — SCMP
- Iluvatar CoreX debuts a supernode with 144 GPUs in one cabinet — SCMP
- Meta's Muse Spark Open, an 816B-parameter MoE coding model (42B active, 1M context), on NVIDIA GB300 NVL72 — NVIDIA
- Chip Industry Week in Review — Semiconductor Engineering
139 items considered: 45 arXiv · 43 RSS · 25 Reddit · 16 OpenAlex · 6 GitHub · 4 crates.io · 0 HN · 0 Hugging Face · 0 PyPI · 0 conferences · 0 USPTO patents · 0 SEC Form D · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed) and one RSS feed failed, so those zeros are not "nothing new" results; the patents and Form D scans were not due this window. Excluded as already covered: Yosys 0.70, the tt-metal v0.80.0 and IREE 3.13.0 release trains. Most of Reddit's items this window were career and interview threads and were out of scope. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.