What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
ArchAgent searches chip, scale-up and scale-out designs with an LLM planner and a deterministic evaluator, and reports 1.93x over a GPU baseline
The framework splits system design into chip, scale-up and scale-out subproblems, each handled by specialist agents under an LLM planner. Every performance number comes from an analytical evaluator rather than from the model, which keeps the grader outside the agent, the same property the last two weeks of agentic-verification papers argued for. On a mixed AI+HPC workload under a 1 MW power budget it finds heterogeneous designs with a 1.93x weighted geometric-mean speedup over a homogeneous GPU baseline, in 18 evaluations against 100 for the comparison search. The result is only as good as the analytical models behind it, and it is one workload. arXiv
IREE 3.13.0 ships with four breaking changes, including a new textual IR syntax for op properties
The release candidates from the last brief are now a final release: 76 PRs since 3.12.0. Op properties in the Codegen, VectorExt, Flow, HAL, LinalgExt, Stream, Util and VM dialects are now written in <...> instead of {...}, so hand-written IR and tuning specs need updating. Scalable vectorization on LLVMCPU now requires --iree-llvmcpu-vscale-range. CUDA targets default to newer PTX versions (sm_120 and sm_121 previously failed to compile at all), and the Python benchmark_module result type changed to BenchmarkResult.report. VMFB bytecode and HAL module versions are unchanged. GitHub
TileDRAM makes tile-to-DRAM placement a compiler-visible layout for 3D DRAM GPUs
Compute-unit-local 3D DRAM designs have no abstraction for how operand tiles are arranged in the DRAM address space, so structured tile accesses can hit row-buffer conflicts under the existing address mapping. TileDRAM extends the GPU Linear Layout abstraction to DRAM placement coordinates and picks a layout per tile access signature by evaluating candidates against row-buffer behavior. The layouts are realized with ordinary address arithmetic, with no new address-remapping hardware. The excerpt we have stops before the evaluation numbers, so we can't say how much it gains. arXiv
HBFSim models High Bandwidth Flash next to HBM and finds HBM is better spent on KV cache than as a flash cache
High Bandwidth Flash promises terabyte-scale accelerator-local capacity at near-HBM bandwidth, but brings NAND latency, out-of-place updates and endurance limits into the memory hierarchy. HBFSim is an event-driven simulator for HBM+HBF systems with host-managed flash translation, driven by a calibrated LLM serving frontend. On Llama-3.1-70B and Qwen3-235B-A22B decoding, HBF serves data that does not fit in HBM 11.0–19.0x faster than host DRAM. The study's pointer is to hold running sequences' KV cache in HBM rather than use it as a cache for flash. Simulation only, for a technology that has not yet shipped. arXiv
BS-Spec derives speculative-decoding drafts from the top bits of a single block-floating-point model
Self-speculative decoding normally needs a separate draft model and KV cache, or fixed draft settings that ignore the workload. BS-Spec builds several draft representations from one BFP target model by loading only the most significant bits of weights and KV cache with shared exponents, picks the precision pair per serving regime by offline calibration, and applies it through a precision lookup table, with a LUT-driven mixed-precision accelerator behind it. The excerpt cuts off before the hardware results, so we can't report the speedups. arXiv
Reddit threads say Tenstorrent raised $1.5B at a $6.2B valuation, with Intel and Qualcomm both reported courting it
Both items are r/RISCV post titles with no body and no linked reporting in hand: one says Tenstorrent announced a $1.5B Series E at a $6.2B valuation, the other that Intel and Qualcomm are courting the company, citing Startup Fortune. We can't confirm the round or the courting from what we have. If the round is real, it is the largest private raise among the open-RISC-V accelerator vendors in our tracking, and it lands a few days after Tenstorrent's Ascalon XG compiler patches. r/RISCV · r/RISCV
Also noted
- CMM-MP, a CXL-plus-Ethernet memory-pooling device, reports 2.7 us latency and up to 23 GB/s, and beats RDMA-based pooling — arXiv
- qGAMMA maps mixed-precision DNNs onto spatial accelerators with a genetic algorithm and a synthesis-calibrated model — arXiv
- GUMPIM proposes reserved contiguous PIM pages to get around memory interleaving and virtual memory — arXiv
- MemLLM does on-device RAG with in-storage acceleration using precomputed KV caches — arXiv
- Understanding LLM hallucinations caused by soft errors — arXiv
- Reports that Nvidia routes all NVHBM base-die production through TSMC 3nm and that Samsung will use TSMC technology for Nvidia's next memory chips, both titles only — r/Semiconductors · r/hardware
- Cadence and Notre Dame on a composable AI-accelerated thermal solver for 2.5D/3D-IC packages — Semiconductor Engineering
- Nanoelectromechanically gated gain-cell eDRAM from UC Berkeley, Samsung and Intel — Semiconductor Engineering
- Ken Shirriff on addition and subtraction microcode in the Intel 8087 — righto.com
- A 5-stage RV32I core taken through Vivado on an Artix-7, with a 7 ps timing miss — r/FPGA
- A 5-stage RV32I core in Verilog with CSR traps and a tagged branch predictor, open source — r/RISCV
- HeyPCB, an MCP server that gives coding agents PCB-engineering tools — GitHub
- eisler-core, a new Rust crate for parsing, DRC, routing and zone fill on KiCad PCB files — crates.io
104 items considered: 20 arXiv · 21 RSS · 29 Reddit · 5 OpenAlex · 5 GitHub · 7 crates.io · 1 HN · 16 Hugging Face · 0 PyPI · 0 conferences · 0 USPTO patents · 0 SEC Form D · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed), so that zero is not a "nothing new" result; the patents and Form D scans were not due this window. Excluded as already covered: the CIRCT firtool-1.162.0 release and the IREE 3.13.0 release candidates. Most of Reddit's items this window were career threads and were out of scope, and the Hugging Face items were repeated quantizations of small Verilog models. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.