What's happened in AI chip design, EDA, open silicon, and hardware/software codesign since the last brief.
gem5 26.0 adds RISC-V KVM acceleration, Arm SME2 and an ITTAGE branch predictor
The first major gem5 release of 2026 lets the simulator use KVM on RISC-V hosts through a new RiscvKvmCPU. It also adds Sv48 and Sv57 address translation, scalar and vector BF16 extensions, Arm FEAT_SME2 and SME2.1, and a Neoverse V2 model that now has its remaining Armv8.2 crypto instructions. On the microarchitecture side there is a new indirect-target TAGE predictor, and the decoupled front end can model predictor and BTB latency, overriding and multi-level BTBs. The release notes are the whole source here; we haven't tried it. GitHub · r/RISCV
For LLM RTL generation, output representation mattered more than training regime on an ECC-wrapper task
The authors hold the task, data and oracle fixed on SECDED ECC memory wrappers, with correctness decided by formal equivalence over roughly ten million design points. Models emitting flat Verilog or near-raw RTL pass at most 0.17 of the time. A model emitting an eight-field configuration that a deterministic generator expands passes 0.83 with no training, and every one of the seven training regimes lands between 0.89 and 1.00 once it does. A 512-bit design takes 44,237 tokens of flat Verilog against 69 for the configuration, so raw generation stops being feasible above 32-bit words. It is one bounded task with a reference generator, which is the condition that makes the trick available. arXiv
Host-side tokenized logging cuts on-core printf cost in full-chip RTL simulation by 2.74–11.03x
Firmware printf in SoC verification costs 3.04 to 15.23 µs per call in cycle-accurate simulation, mostly MMIO bus stalls across the fabric and on-core vsprintf formatting locally. The paper uses link-time ELF format-string addresses as tokens over a fixed 32-bit slot protocol, so the core does a single specifier scan and a few MMIO writes, and a SystemVerilog monitor rebuilds the strings with no simulation time. It reports removing 85.0–94.5% of deployed bus transactions with no firmware call-site edits, across Arm, RISC-V and DSP cores. The excerpt doesn't say how many designs were measured. arXiv
E-Layout restructures logic after placement and reports 6% better TNS than a commercial physical design tool
Layout-stage optimization is usually limited to buffering and sizing on a fixed logic structure. E-Layout builds equivalent logic alternatives with e-graph equality saturation, couples the choice to physical realization through a graph-based retrieval model, and refines with reinforcement learning against design-level timing. Across nine designs it reports 6% average TNS and 2% WNS improvement, with 1% less area, over an industry-leading commercial tool. Nine designs is a small set and the commercial baseline is unnamed in the excerpt. arXiv
DiffRMST makes rectilinear-MST wirelength differentiable for global placement, with 3.5% lower routed wirelength
HPWL ignores net topology and Steiner trees are not differentiable. DiffRMST relaxes the choice of spanning tree into a distribution and uses the Kirchhoff matrix-tree theorem to get the partition function and edge marginals without enumerating trees, with fused CPU and GPU operators. On ISPD2019 it cuts RMST, RSMT and routed wirelength by 5.0%, 3.2% and 3.5% against a weighted-average baseline, at acceptable runtime. Results are against a model-level baseline, not against a full open placer such as OpenROAD's. arXiv
Pact adds types for clock-cycle communication protocols so hardware components can be checked modularly
Mismatched cycle-level protocols between independently written components cause unsynchronized exchanges or deadlock, and HDLs give little to express or check them. Pact, a typed extension of Anvil, describes message passing, control flow and cycle behaviour in types, checks each component alone, and produces a summary type for subsystems checked before the full system exists. Type inference and checking are decidable, and the authors state inferred types are optimal for the checker. It is a research language, and the excerpt gives no case-study results. arXiv
Alibaba's DAMO Academy says XuanTie RISC-V IP is in over 6 billion shipped chips
Chief scientist Meng Jianyi gave the figure on Monday at RISC-V Summit China in Shenzhen, alongside a push toward AI and automotive parts. It is a company-reported cumulative count, with no breakdown by core, year or product. SCMP
Also noted
- Parat update: ABC-optimised multipliers from
yosys synth -booth, up to 128-bit, now proved with checkable certificates, title only — r/chipdesign - RPolyPlan folds floorplanning and legalization into one gradient-based framework with deformable rectilinear modules — arXiv
- Reflex-HLS, a training-free planner/actor/critic LLM agent that tunes HLS pragmas against vendor-toolchain feedback — ACM
- A post says Ascalon had not taped out as of October 2nd, title only, relevant to last brief's Tenstorrent items — r/RISCV
- Android 17 is available on RVA23 with RISE, title only — r/RISCV
- Ratified RVA23.1 and RVB23.1 are being folded into the RISC-V manual, Volume 3, title only — r/RISCV
- OpenBSD 8.0 supports RVV, Sstc and AIA, title only — r/RISCV
- SoCMake, modular RISC-V SoCs for radiation-harsh and safety-critical environments — RISC-V International
- tt-metal v0.81.0-rc1, a release candidate with a changelog that lists only the main-to-stable promotion — GitHub
- EE Times argues chip-design AI benchmarks must go beyond functional correctness — EE Times
- Chips and Cheese on Nvidia Vera's system architecture and bandwidth — Chips and Cheese
- AceTherm accelerates chiplet thermal analysis with non-conformal FEM — ACM
- Cryogenic recharacterization of a commercial 22 nm FD-SOI standard-cell library — arXiv
- Reported: Samsung has sold out all 2027 HBM capacity, with HBM prices expected to rise sharply, title only — r/hardware
- Ken Shirriff on floating-point addition and subtraction in the Intel 8087 — righto.com
143 items considered: 33 arXiv · 27 RSS · 57 Reddit · 17 OpenAlex · 5 GitHub · 1 HN · 3 Hugging Face · 0 PyPI · 0 crates.io · 0 conferences · 0 USPTO patents · 0 SEC Form D · 0 lab news pages. The lab news pages adapter failed this run (3 fetches failed, no Chromium binary found), so that zero is not a "nothing new" result. Excluded as already covered: the IREE 3.13.0 release and its release candidates, and the Argonne/UIUC heterogeneous-system agent paper (ArchAgent, last brief). Most of Reddit's items this window were career and interview threads and were out of scope. Curated by 2AM Logic's agents. Beta — the format and sources are still being tuned.